Lecture 8: Datapath II

1
Lecture 8 Datapath II

• Last Time
• Elements of Logic Design
• Architectural Building Blocks
• Simple MIPS implementation
• Today
• More instructions on simple datapath
• An alternative datapath
• Control Logic
• Single-cycle datapath

2
Instruction Execution
I-Fetch

• 5 basic steps
• fetch instruction (IF)
• decode instruction (ID)
• fetch operands (OF)
• execute (EX)
• store result (RS)

Decode
O-Fetch
Execute
Save Result
3
ADD The Movie

• IR lt- MPC, A lt- BUS lt- PC
• A lt- RIR.RS1, B lt- RIR.RS2, PC lt- BUS lt- A
  4
• RIR.RD lt- BUS lt- A B

opcode
MAS
LIR
RW
LA
LPC
MW
AS
AF
Z
A
IR
Reg File
PC
MEM
A
LB
BS
DO
B
EA
EI
DI
EM
EPC
4
ADD The Movie (2)

• IR lt- MPC, A lt- BUS lt- PC
• A lt- RIR.RS1, B lt- RIR.RS2, PC lt- BUS lt- A
  4
• RIR.RD lt- BUS lt- A B

opcode
MAS
LIR
RW
LA
LPC
MW
AS
AF
Z
A
IR
Reg File
PC
MEM
A
LB
BS
DO
B
EA
EI
DI
EM
EPC
5
ADD The Movie (3)

• IR lt- MPC, A lt- BUS lt- PC
• A lt- RIR.RS1, B lt- RIR.RS2, PC lt- BUS lt- A
  4
• RIR.RD lt- BUS lt- A B

opcode
MAS
LIR
RW
LA
LPC
MW
AS
AF
Z
A
IR
Reg File
PC
MEM
A
LB
BS
DO
B
EA
EI
DI
EM
EPC
6
Jump (J)

• IR lt- MPC, A lt- BUS lt- PC
• PC,A lt- BUS lt- A 4
• B lt- BUS lt- IR.CONST26
• PC lt- BUS lt- A B

opcode
MAS
LIR
RW
LA
Z
LPC
MW
AS
AF
A
IR
Reg File
PC
MEM
A
LB
BS
DO
B
EA
EI
DI
EM
EPC
7
Branch Execution (BEQZ)

• IR lt- MPC, A lt- BUS lt- PC
• PC,B lt- BUS lt- A 4, A lt- RIR.RS1
• if(Z)A lt- BUS lt- IR.CONST16
• PC lt- A B

opcode
MAS
LIR
RW
LA
Z
LPC
MW
AS
AF
A
IR
Reg File
PC
MEM
A
LB
BS
DO
B
EA
EI
DI
EM
EPC
8
Load Execution (LW)

• IR lt- MPC, A lt- BUS lt- PC
• A lt- RIR.RS1, PC lt- BUS lt- A 4 // could
  load B
• B lt- BUS lt- IR.CONST16
• A lt- A B
• RIR.RD lt- BUS lt- MA

opcode
MAS
LIR
RW
LA
Z
LPC
MW
AS
AF
A
IR
Reg File
PC
MEM
A
LB
BS
DO
B
EA
EI
DI
EM
EPC
9
Store Execution (SW)

• IR lt- MPC, A lt- BUS lt- PC
• A lt- RIR.RS1, PC lt- BUS lt- A 4 // could
  load B
• B lt- BUS lt- IR.CONST16
• A lt- A B, B lt- RIR.RD
• MA lt- B

opcode
MAS
LIR
RW
LA
Z
LPC
MW
AS
AF
A
IR
Reg File
PC
MEM
A
LB
BS
DO
B
EA
EI
DI
EM
EPC
10
HP Datapath

• Simple Datapath with control signals (Figure
  5.32)
• Datapath with full controls (Figure 5.33)
• Note that this datapath has no shared busses!
• What are the implications?

11
MIPS Instruction Formats
R rd ? rs1 op rs2
I ld/st, rd ? rs1 op imm, branch
J j, jal
Fixed-Format (MIPS)
12
Control Logic
ALU
Fetch Instruction
Access Registers
Write Result

• View datapath as a programmable machine
• Control logic is the program
• Control signals are the primitives for the
  programming language
• RTL is the program (for each instruction)
• Can use a Finite State Machine for control logic

13
Control Signals For ADD
ALU
Fetch Instruction
Access Registers
Write Result

• IorD 0
• MemRead 1
• IRWrite 1
• ALUSrcA 0
• ALUSrcB 01
• ALUOp ADD
• PCSrc 00
• PCWrite 1

14
Control Signals For ADD
ALU
Fetch Instruction
Access Registers
Write Result

• No control signals need be asserted

15
Control Signals For ADD
ALU
Fetch Instruction
Access Registers
Write Result

• ALUSrcA 1
• ALUSrcB 00
• ALUOp ADD

16
Control Signals For ADD
ALU
Fetch Instruction
Access Registers
Write Result

• MemtoReg 0
• RegWrite 1
• RegDst 1

17
Full Control State Machine

• Figure 5.42 from text

18
Single Cycle Datapath

• Figure 5.17 from HP
• Can execute instructions in 1 step!!!!!
• What are the implications?

19
Summary

• Today
• More instructions
• Control Logic
• Next Time
• Control logic optimization
• Introduction to pipelining