Title: Analog Digital VLSI Design Reference Current Voltage
1Analog Digital VLSI DesignReference Current /
Voltage
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3Reference voltage/ current
4Requirements
5Characteristics
6Sensitivity
gain
7Sensitivity
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9How to generate bias current?
- Generate stable Vref directly
- Generate stable Iref, use it to generate voltage
- Generate stable Iref, and mirror it.
Vref
10References
11Passive reference voltage gen. ckts.
12Active referencesvgs referenced
Vref 1/3 Vdd 1/ 3 Vds S 1
Not much gain
13Vgs referenced
14Another approach
v1
1
Iout is not independent of variations in Vdd
15Cascoding
16Modified Vgs referenced
17Vbe referenced
18Modified Vbe referenced
19Observations
- Sensitivity of the voltage across an active
device can be less than 1 - How to design a Vref/ Iref independent of Vdd?
20Self bias
- Generate Vref across an active device
- Using Vref generate a current Iout
- Use Iout to force the current into the reference
active device
21Concept
Forces Iin decided by Iout
Iin
22Current dec.
If vdd increases, current tend to increase
Voltage reduces
Node voltage increases more to inc. the current
Node voltage decreases Current rolls back
23Vdd insensitive
- Self bias circuit
- But it is not temperature insensitive
24Cascoding improves sensitivity
25Temperature insensitivity measure
Example
26- Now we modify self bias to force a unique current
- 3 methods
- Using R
- Using BJT
- Using MOS
- For we will compute Tcf, vddS vref
27Force a desired current using R
This loop will always try to negate variations
in Vdd
Modification to force a unique current
Vdd independent But process and temperature
dependent K should be gt1
28Tcf
29Sensitivity to Vdd
?
?
Make L large
30Start up problem
Initially Vdd
Conducts initially As Vx increases, M5 stops
conducting
vX
Initially gnd
31Remarks
- Vref Vgs1- Vgs2
- Can we make Vref a Vgs1?
- Can we have K1?
32Using MOS - Vt referenced K1
earlier Vref difference of two Vgs.
Loop to stabilize current But Bias is required,
shd. come from reference arm Now M2 becomes
redundant as M5 makes M1 diode connected So,
remove M2
5
33Self bias- Vt referenced
Start up circuit
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35Vdd sensitivity
36sensitivity Calculation
37Tcf
38Using BJT--Vbe referenced
39Vbe referenced in CMOS
40Vbe referenced in CMOS
CTAT CURRENT
41Tcf calculations
42calculation
43Vth referenced self bias
PTAT CURRENT Is becomes n times
Shd. Be equal
44Another circuit
Ckt to make x , y node voltages equal
45Temp insensitive reference
- Can we add PTAT and CTAT current to get temp
insensitive reference?
46So, two ways
47Temp insensitive Reference voltage
Vref
48Temp. plot
49Cascoding
50Vref to Iref conversion
51Better compensation
52Performance Obtained
The Performance achieved by the circuit is as
follows
53Temperature Sweep
54All mos CURRENT reference
55CONCEPT
Vt temp dependence
Negative constants
µ temp dependence
Drain current
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57,Obtain Vgs
58Vov. dominated
Mobility dominated
Choose 2 Vgs on both sides of ZTC point
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60Operation
61Core circuit
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66Temperature insensitive
67Vbe referencedBJT only
Thermal voltage 25 mV
Iin Iout
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