LABORATOIRE DE MICROELECTRONIQUE BATIMENT MAXWELL B-1348 LOUVAIN-LA-NEUVE BELGIQUE

1
LABORATOIRE DE MICROELECTRONIQUEBATIMENT
MAXWELL B-1348 LOUVAIN-LA-NEUVE BELGIQUE
An Approach to the Design of Analog Fuzzy Logic
Controllers in CMOS Technologies
Implementation, Test and Application  Carlos
Dualibe
2
FUZZY LOGIC Formalism for codifying Human
Reasoning within a Numerical
Framework.FUZZY SYSTEM Model-Free Universal
Approximator. Structured Knowledge Base
(if-then rules)
Usefulness To solve problems that are either
difficult to tackle mathematically or
where its use provides improved performances
and/or simpler implementations.
Engineering Applications -Process and
Environmental Control (examples)
-Robotics and Automation
-Automotive Industrial Applications
-Signal and Image Processing
-Power Electronics -
3
Hardware Implementation Choices for Fuzzy
Controllers
Allocation of the applications in the space
Complexity Time Response
Allocation of hardware solutions in the space
Complexity Time Response
Intended Target Applications Signal and Image
Processing, Power Electronics
4
Why Analog?

• Fuzzy Processing is analog in nature.
• Usual applications demand reduced accuracy.
• Low Power and/or High Speed
• Reduced Complexity Small area No need of A/D
  and D/A
• to interface Sensors and Actuators
• Ideal for Embedded Subsystems.

• Main Goals of this Work
• Comprehensive study of the Analogue Fuzzy
  Operators
• Design and Test of Programmable Architectures for
  Analogue Fuzzy Controllers

• Secondary Goal
• To undertake preliminary studies of an embedded
  Fuzzy Logic application
• in the field of Signal Processing.

5
Fuzzy Controller Architecture and Fuzzy
Algorithms
R1

• Building Blocks
• Membership Functions
• T-Norms T-CoNorms
• Consequents
• Defuzzifiers

R2
Suits optimal for Hardware Implementation !
Fuzzy Controller
6
Membership Functions Circuits -Trapezoidal
Shapes Based on Triode Transconductors
TYPE I Differential Regulated Cascode Triode
Transconductor
Transfer Curve Slope?gm Crossover?Vk
Circuit M1, M2?Triode
Non-Symmetric Diff. Amp. DA1,DA2
(W/L)Md1 gt (W/L)Md2
Vds
Vds
7
Membership Functions Circuits (2)
TYPE II Single Regulated Cascode Triode
Transconductor
Transfer Curve Slope?gm
Knee?V2Vk n Vds/2
Circuit M1?Triode M2? Saturated
Vds
n Subthreshold slope factor
M2 Large size transistor aimed for
setting a conduction threshold
8
Membership Functions (3) Four Independent
Parameters ? 2 slopes (gm1, gm2) 2 Crossover
(Vk1 , Vk2)
Iout1
Iout2
gm2
gm1
Vk1
Vk2
Vin
Io
Io
Complementary FMF (CFMF)
Direct FMF
9
Membership Functions Circuits (4) Comparison
against saturated transconductor

• Analogue Programming Electrically Tunable
  Slopes by setting Vds
• Discrete Programming large slope range is
  optimally allowed by a set of (W/L)s
• Small Slopes can be set by using small Vds
  rather than very long channel Transistors
• Increased Current Consumption (Differential
  Amplifiers at the Regulation loop)
• More sensible to Mismatch (Triode transistors?
  ?Vds)

Triode
Saturated
10
Membership Functions Circuits (6) Full
Programmable Compact Fuzzy Partition
(Based on 1)
SPICE simulation for a 7-label Circuit Io
10?A, Vdd5V
Slopes?Vs1,Vs4 - Crossover points ?
Vk1ltVk2ltVk4
Reduced number of transconductors Reduced Current
Consumption Cumulative mirroring errors and delay
due to cascading
1 Willamosky B. et al, ANNIE96
11
T-Norm and T-CoNorm circuits General Requirements
In1
T-Norm or T-CoNorm
Out
InN

• Multiple inputs (N)
• O(N) Complexity ? Size and consumption
  proportional to N
• Parallel Processing ? No cascade tree of
  binary operators
• Inputs Transparency ? Same load at each
  input - Same input/output delay

Circuits - Improved Lazzaros WTA-MAXIMUM -
Mixed-Mode O(N) MAXIMUM - O(N2) LTA-MINIMUM -
O(N) LTA-MINIMUM
12
T-Norm and T-CoNorm (1) Lazzaros WTA-MAXIMUM
Improved Version
Concept
Systematic Errors 1.6

• N current-controlled voltage-sources ( M1, M2 )
  fighting in parallel
• Propagation error ? ? Early effect in M2 (? Mo)
• Discrimination error ? ? Early effect in M2 - ?
  inversion degree of M1
• Mismatch error ? VT and ? of M2, Mo

13
T-Norm and T-CoNorm (2) Lazzaros WTA-MAXIMUM
Delay Undershot Improvement!
E

I15?A I2pulse 3?A to 7?A - 100ns
14
T-Norm and T-CoNorm (3) Mixed-Mode MAXIMUM
Systematic Errors 2.3

• Set of N Source Followers fighting in parallel
• Propagation error ? ? Voff offset of A
• Discrimination error ? ? Ao DC gain of A
• Mismatch errors ? due to ?Voff mainly

Distribution of Input Signals achievable in
voltage-mode !!
15
T-Norm and T-CoNorm (4) New O(N2) LTA-MINIMUM 2
2-Input MINIMUM
2-Input LTA MINIMUM
Systematic Errors 3

• Parallel comparison between input currents -Vdd
  limits the number of inputs
• Propagation error ? Due to the Early Effect in
  transistors Mp
• Discrimination error ? ? with the impedance of
  internal nodes (i.e. V2)
• Mismatch errors ? Associated with mirrors Mn and
  Mp

2 Dualibe, Jespers, Verleysen, IEEE ISCAS2001
16
T-Norm and T-CoNorm (5) New O(N) LTA-MINIMUM 3
Improved Version with current feedback
Ii Mirror
Concept

• N current-controlled voltage sources (Cells-i)
  fighting in parallel
• Current feedback improves accuracy of the
  MINIMUM ( enhanced Wilson mirror)
• Systematic error (0.4)
• Mismatch error due to ?VT and ?? of M5, M6

3 Donckers, Dualibe, Verleysen, IEEE
ISCAS2000
17
Defuzzifiers Closed Loop Defuzzifiers
Voltage mode
Current mode

• Complexity increases with the
• number of rules
• May need frequency compensation
• due to feedback ? speed

• FMF or T-Norms gain must be controlled
• May need frequency compensation
• due to feedback ? speed

18
Defuzzifiers(2) Open Loop Defuzzifiers
Divider
Pseudo-Normalizer

• Complexity may increase with the number of rules
  (i.e.R1.Rm)

• Only one extra mirror per rule to compute
  denominator

19
Defuzzifiers(3) Open Loop Defuzzifier with
Divider Common Weighting strategy for
digitally programmable singletons.

• n mirrors per singleton
• Silicon surface and input capacitance of each
  singleton result much smaller than in the local
  weighting approach (i.e. (2n/n) times reduced)
• Only one D/A- Can be optimized to get desired
  accuracy
• Simplicity

20
Defuzzifiers(4) Novel Two-Quadrant Analog
Divider 4

• M1 M2M3?triode
• ?
• Input Nodes Nd and Nn become resistive!
• Thus
• Vout-Vbo (Vb1-Vbo) (IN/ k ID)
• Current/input voltage/output ?IDEAL!

Nn
Nd

• Systematic errors - Mainly due to mobility
  reduction in triode transistors M1, M2, M3.
• - Gain error and offset can be
  neglected if cascoded PMOS mirrors
  are used (M7, M8, M9).
• Mismatch errors -For small current ID, strongly
  influence of mismatch of VT between
  transistors M4,M5,M6.

4 Dualibe, Verleysen, Jespers, IEE Electronics
Letters, 1998.
21
Defuzzifiers(5) Two-Quadrant Analog
Divider-Measurement
() Measured (-) Calculated
Relative errors vs. ID 2 ?A lt IN lt 8?A 10?Alt
ID lt30?A
(Vout-Vbo) vs. IN 0lt IN lt10?A 10?Alt ID lt30?A
Non-Linearity
22
Defuzzifiers(6) Comparison Against other Dividers
Wiegerink R., Kluwer A. P., 1993

• Inputs must be supplied at different nodes
• at least twice?Additional mirroring errors
• NL 1

Huertas et al, Trans. Fuzzy Systems, 1996

• Need extra I-to-V converter
• Differential currents inputs
• NL 1 (only divider)

Divider
Current-to-voltage converter
23
Defuzzifiers(7) Electrically Programmable
Singletons
New Electrically Tunable Linear Current-Mirror
Spice Simulation 1VltVb2lt1.5V
Other Approach Sasaki et al, 3th Int. Conf. On
Industrial Fuzzy Control and Intelligent
Systems 1993
24
Estimation of the global accuracy of the
Controller
Only One Fired Rule 2 lt ?Vout/Vout lt3
Unrealistic!
Divider
Singletons D/A
Mirror
?Vout

25
Estimation of the global accuracy of the
Controller(2)
Two Fired Rules in a complementary way 2.5 lt
?Vout/Vout lt3.5
?Vout for 0.1lt ?1 lt 0.9 ?20.9
() Divider (o) CFMFT-NormIo
25
26
Programmable Fuzzy Architectures General
Guidelines

• Standard CMOS Technologies? Mixed Signal ?
  Analogue Processing Digital Programming
• Current-Mode vs. Voltage-Mode Current Mode
  Voltage Mode
• Analog Computation. -
• Signal Routing...-
• Chip external Interface.. -
  
• MIXED MODE
• Building Blocks Interface Avoid the use of
  extra V-to-I or I-to-V converters?Improves Delays
  and Accuracy.
• Modularity Share operators (i.e
  Membership Functions Circuits, Common weighting)
• Transistors Sizing Large size ?Good
  Matching?Poor Integration Density (dedicated
  controllers)
• Small size ?Poor Matching?Good
  Integration Density (programm. controllers)
• Programmability can help to relax sizing
  requirements for a given accuracy!

27
A 9-Rule 2-Input 1-Output Programmable Fuzzy
Controller 6

• Zero-Order Controller-Fixed Number of Rules (Grid
  Partition)
• Complementary MF Labels (Type II Three per
  input)
• T-Norm Complemented Lazzaros MAXIMUM
• Defuzzifier Common weighting
• Discrete Programming of Antecedents and
  Consequents
• Intended for embedded applications

6 Dualibe, Jespers, Verleysen, IEEE
ISCAS2000
28
9-Rule Fuzzy Controller (1) Membership Function
Programming
Linear Resistor

• Measured CFMF Type-II
• Io10?A Vdd5V
• Input Range 1.5VltVinlt4.5V

Half CFMF Type-II

• Local setting of analog parameters
• s0..s3?Slopes (2x4-bit)
• p0.p4?Knees (2x5-bit)

29
9-Rule Fuzzy Controller (2)Test Result
TARGET
MEASURED
Relative Error Surface
Relative Error Distribution
Settling time (90) S.Signal
190ns L.Signal 450ns
30
9-Rule Fuzzy Controller (3)Comparison
Programmability






MF Knees

fixed

on chip (6b)

off chip

on chip (6b)

off chip

on chip (5b)

MF Slopes

fixed

fixed

on chip (4b)

on chip (2b)

fixed

on chip (4b)

Consequents

fixed

on chip (6b)

off chip

on chip (4b)

on chip (4b)

on chip (5b)


31
Application Example Fuzzy Control of a DC/DC
Buck Converter9

PWM duty cycle
Dp, Di Highly Nonlinear functions Small
Steady-State Error and Fast Settling Time for RL
Changes
(9 Franchi E. et al., IEEE JSSC, June 1998)
32
Application Example(2) Fuzzy Control of a DC/DC
Buck Converter10
Optimal Control Surfaces
DI 1 Input-1 Output 4 Rules
DP 2 Inputs-1 Output 4 Rules
(10 Rashid M., Power Electronics-Circuits,
Devices and Applications, Prentice Hall, 1993)
33
A General-Purpose Programmable and Reconfigurable
Fuzzy Controller
N ? 5 Q ? 3 M ? 27 F ? 16

• CFMF type-II
• Programmable MAXIMUM mixed mode O(N)
• SWITCH MATRIX smartly wired

34
General-Purpose Controller (2) First-Order
Output Configuration
Divider
Consequent Rule-i?
Novel High-Input Impedance Voltage Mode Adder
Defuzzified?Value
35
General-Purpose Controller (3) Zero-Order Test
Result
Rules Map
Measured Surface
Relative Errors
a)
b)
Settling time (90) S.Signal
570ns L.Signal 1100ns
36
General-Purpose Controller (4) 4-rules
First-Order Controller Test Result
Measured CFMF
Measured Surface
ANFIS Fitting A comparison

• 1st-Order 4-rules
• 28 parameters
• RMSE 0.8

• Zero-Order 4-rules
• 20 parameters
• RMSE 2

• Zero-Order 9-rules
• 33 parameters
• RMSE 1.4

37
COMPARISON
38
General Purpose Controller (6)Further
Improvements
?Cox Early
AVTo CMOS 2.4? 50 ?A/V 10V/? 24mV
? CMOS 0.8? 100 ?A/V 10V/? 12mV ?

• Scaling to Modern Technologies

A) Analog Circuits
Silicon Area
Same Current
Same Vdd, VTo
?2
?2
-Same L (keep same Early) -W ? W/2 gt50 Area
Reduction
Mismatch
B) Digital Circuits theoretical scaling factor
(1/9). Let us assume (1/4.5).
Total Area Reduction 39.5mm2 ? 13.6mm2
39
Time-Domain Signal Analysis Using Fuzzy Logic and
its Application to Self-Adaptive Channel
Equalization
General Setup
Built-in Oscilloscope inferred Assertions
could be used for adaptation, detection, testing,
etc.
40
Continuous-Time Self-Adaptive Equalization based
on the Eye-Pattern 8 System Architecture
B)
A)
E(s) (s-z) (sz)
Adaptive Equalizing System
Control Surface related to the Eye Pattern

• On-Chip Real-Time Scope ? SIGNAL ?2D-FIGURE
  (EYE PATTERN)
• Controllers Decision Making Keep ACTUAL EYE
  within AREA TOLERANCE
• Controllers Output ? EQUALIZERS ZEROS PLACEMENT

8 Dualibe, Jespers, Verleysen, IEEE
ISCAS2001
41
Fuzzy Logic Controller Rule Base and Input
Partition
Boosting must Decrease
Area Tolerance
Boosting must Increase

• RULE BASE 25-Rules controlling Equalizer
  Amplitude Boosting (5-labels per input)
• Area Tolerance immunity to NOISE, RINGING,
  PULSE SHAPE, ETC

42
Architecture of the Fuzzy Controller

• Zero-Order Sugeno 25 rules
• Fuzzifiers 5-Labels per input.
• T-Norms 2-input MINIMUM (O(N2) )
• Defuzzifier Averaged Weighted Sum
• Discrete Programming of singletons (5-bits)

43
5-Labels Fuzzy Partition Circuit
Vin
SPICE simulation for Io10?A

• Chained differential pairs low consuming, small
  area and compactness
• Vk1ltVk2lt..ltVk4 fix the crossover points
• Fixed slopes at mask level by transistors Ma size

44
Fuzzy Controller Test Results
Fuzzy Logic Controller Fuzzy Logic Controller
Technology CMOS-2.4?
Complexity 25-Rules 2-inputs 1-output
Power Supply 5V
Power Consumption 4.4mW
Area Analog 2.9 mm2 Digital 1.1 mm2
RMSE 4.5
Input/Output Delay (90 Steady State) S. Signal 380ns L. Signal 900ns
Measured
Target
45
Fuzzy Controller Improvement
Vs
R3
R2
R1
R4
R6
R5
R7
R8
R9
R11
R10
Vt

• Use Tree Partition for the input space to
  minimize rules set ? ONLY 11 Rules
• Input Vs? Compact 5-Label Fuzzy partition circuit
• Input Vt? Six individual Membership Functions

46
Amplitude-Boosting Gm-C Filter
Bi-Quad Filter
A)
Amplitude

Phase

• gm1gm3gm5gmmax?fix
• gm2gm4?tunable up to gmmax
• Symmetric Zeros at

Theoretical Frequency Response
47
New Full Electrically Tunable Triode
Transconductor 9
Transconductance

• Linear tuning?Iz
• Phase error lt 2

Transconductor
Divider
CMFB with adaptive Bias Io 10
Improved common-mode voltage
stability upon tuning.
CMFB
9 Dualibe, Jespers Verleysen IEEE ISCAS2001
10 DeLima, Dualibe, IEEE ISCAS2000
48
Equalizing Filter Test Results
BiQuad Gm-C filter BiQuad Gm-C filter
Technology CMOS-2.4?
Power Supply 5.5V
Power Consumption 22.6mW (nominal) (Iz25 ?A )
Area 5.3mm2
Max. Boost 30dB (_at_7Mhz.)
Tuning range 15?Alt Iz lt 35?A
Measured AC Response
49
Cable Equalization (simulations)
A1)
A2)
B1)
B2)
Kz evolution for L120, 240, 360m
Eye Pattern before and after the equalizer
Signals for L360m Fs 5Mb/s
Cable CAT5 UTP
50
Adaptation Performance for Noisy Channels
Kz Evolution during adaptation
Our Approach
Widrow 85
Noise Mean0 -Variance0.03
51
Self-Adaptive Equalization Conclusions

• Robust Adaptive Equalization Area Tolerance
  filters out noise, ringing, etc.
• Fuzzy Logic Allows easily the Analog
  Implementation of highly non-linear control
  functions.
• Time-Domain Signal Analysis using Fuzzy Reasoning
  On-Chip Oscilloscope ? Applications beyond
  Channel Equalization topic
  detection, on-chip analog testing, etc

52
CONCLUSIONS Fuzzy Logic Non-Linear Analogue
Design

• Systematic Approach for Analogue Non-Linear
  Synthesis.
• Very Easy to Understand!
• Available Optimization and Design Tools (i.e.
  ANFIS).
• Invariant Network Structure independent on the
  function to synthesize (i.e if-then rules).
• Possibility of programmable devices built by
  standard blocks (Fuzzifiers, Inference Operators
  and Defuzzifiers).
• ?
• Fuzzy Logic must take a place in the Toolbox of
  Analogue Designers for the synthesis of
  non-linear circuits!!