ECE 491 Senior Design I

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ECE 491 - Senior Design I

• Lecture 13 - ASM Diagrams
• Fall 2004

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
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Announcements

• 2 tutors needed for Junior Electronics - contact
  Prof. Wey if interested
• Registration for Spring 2005
• Advising available Friday 11-130, Monday 11-2
• Online registration starts Tuesday

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Where we are

• Last Time
• Discuss Lab 5 - Manchester Code transmitter
• Drivers and Receivers
• Today
• More about Lab 5 - Test Circuit
• ASM Diagrams - an alternative to bubble and
  arrow diagrams

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Reiew - Manchester Code
0
1
1
1
0
0
idle
idle
Manchester
cell

• Note addition of idle value - neither 1 or 0

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Lab 5 - Manchester Transmitter
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Manchester Transmitter Operation
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Testing Your Design

• Step 1 Self-Checking Testbench
• Single byte
• Multiple byte (with no gaps)
• Step 2 Hardware in FPGA
• Inputs allow transmission of 1-4 bytes
• Instantiate with design on S3 board

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Hardware Test Module
Available at foghorn.cadlab.lafayette.edu/ece491/e
xamples/mxtest.v
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ASM Diagrams

• ASM Algorithmic State Machine
• A flowchart notation for state machines
• Motivation
• High-level description of clock-cycle level
  behavior
• Alternative to traditional state diagrams
• Easier to read for large diagrams
• Prevents inconsistent diagram specifications
• More concise than Verilog code

Christopher R. Clare, Designing Logic Using
State Machines, McGraw-Hill, 1973
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Flavors of ASM Diagrams

• Low-level
• Cycle-by-cycle timing
• Detailed specification of input / output values
• Equivalent to standard state diagram
• Register-Transfer Level
• Cycle-by-cycle timing
• Abstract operations (can map directly to low
  level)

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ASM Elements
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Describing an ASM State
Note all other outputs are 0!
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State Description w/ Complex Branches
State Diagram Equivalent (Fill In)
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ASM Diagram Pitfall

• Conditional output boxes specify values
• Conditional output boxes dont specify sequence

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ASM Example - Successive Approximation Circuit
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ASM Example - Successive Approximation Circuit
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ASM Example

• ASM Diagram for Successive Approximation Circuit

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Example MIPS Multicycle Design
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Example MIPS Multicycle Design
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Multicycle Control - ASM Diagram Part 1
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Multicycle Control -ASM Diagram Part 2
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Multicycle Control -ASM Diagram Part 3
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3
4
RTEX
BR
ALUSrcA 1 ALUSrcB 00 ALUOp 10
ALUSrcA 1 ALUSrcB 00 ALUOp
01 PCWriteCond PCSource 01
RTWB
RegDst 1 RegWrite MemtoReg 0
0
0
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Register-Transfer Level ASM Diagrams

• Key idea
• Use same notation as regular ASM
• Instead of outputs, write register transfers
• Advantages
• Plan complex designs before details are nailed
  down
• Estimate resource costs by counting operations in
  each state

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Multicycle Control - ASM Diagram Part 1
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Multicycle Control -ASM Diagram Part 2
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Multicycle Control -ASM Diagram Part 3
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ASM Homework

• Due Thursday 10/28/04
• Create a bubble and arrow state diagram of your
  receiver design FSM
• Create an ASM diagram of your receiver design FSM
• Draw and label neatly for full credit

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Coming Up

• Synchronization Issues with Multiple FSMs
• Manchester Receiver Design

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Ethernet

• Connects computers in a local area network
• Computers communicate on shared wires (ether)
• Distributed control
• Information passed as packets

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Packet Format

• Preamble - used for synchronization
• Destination address - where packet is going
• Source address - where packet is from
• Data
• Error checking - CRC code

Preamble
Src Addr
Dest Addr
Data
CRC
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Mechanisms

• Carrier detection - detects when data is being
  sent
• Interference detection - detects collisions
• Packet error detection - CRC check
• Truncated packet filtering
• Collision consensus enforcement

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Where Were Going - WimpNet 2004

• Scaled-down Ethernet interface
• Medium twisted pair
• Encoding Manchester
• Details to follow, but based on the experimental
  ethernet described in the Metcalfe Boggs paper

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Course Map