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ECE6130: Computer Architecture: Instruction Level Parallelism ILP

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11. 01. 10. 00. 3. Correlating Branch Predictors. Dynamic Hardware Branch Prediction: ... branch b2 (bb!=2) DADD R2,R0,R0 ;bb=0. L2: DSUBUI R3,R1,R2 ;R3=aa-bb ... – PowerPoint PPT presentation

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Title: ECE6130: Computer Architecture: Instruction Level Parallelism ILP


1
ECE6130 Computer ArchitectureInstruction Level
Parallelism (ILP)
  • Dr. Xubin He
  • http//iweb.tntech.edu/hexb
  • Email hexb_at_tntech.edu
  • Tel 931-3723462, Brown Hall 319

2
Dynamic Hardware Branch Prediction
  • Dynamic Hardware Branch Prediction control
    dependences rapidly become the limiting factor as
    the amount of ILP to be exploited increases,
    which is particularly true when multiple
    instructions are to be issued per cycle.
  • Basic Branch Prediction and Branch-Prediction
    Buffers
  • A small memory indexed by the lower portion of
    the address of the branch instruction, containing
    a bit that says whether the branch was recently
    taken or not simple, and useful only when the
    branch delay is longer than the time to calculate
    the target address
  • The prediction bit is inverted each time there is
    a wrong prediction an accuracy problem
    (mispredict twice) a remedy

Taken
Not taken
Predict taken
Predict taken
11
10
Taken
Taken
Not taken
Not taken
Predict not taken
Predict not taken
01
00
Taken
Not taken
3
Correlating Branch Predictors
  • Dynamic Hardware Branch Prediction
  • Correlating Branch Predictors
  • The behavior of branch b3 is correlated with the
    behavior of branches b1 and b2 (b1 b2 both not
    taken ? b3 will be taken) A predictor that uses
    only the behavior of a single branch to predict
    the outcome of that branch can never capture this
    behavior.
  • Branch predictors that use the behavior of other
    branches to make prediction are called
    correlating predictors.

4
  • Dynamic Hardware Branch Prediction
  • Correlating Branch Predictors

5
  • Dynamic Hardware Branch Prediction
  • Correlating Branch Predictors
  • The standard predictor mispredicted all branches!
  • A 1-bit correlation predictor uses two bits, one
    bit for last branch being not taken and the other
    for taken (in general the last branch executed is
    not the same instruction as the branch being
    predicted).

6
  • Dynamic Hardware Branch Prediction
  • Correlating Branch Predictors
  • With the 1-bit correlation predictor, also called
    a (1,1) predictor, the only misprediction is on
    the first iteration!
  • In general case an (m,n) predictor uses the
    behavior of the last m branches to choose from 2m
    branch predictors, each of which is an n-bit
    predictor for a single branch.

Branch address
2-bit per-branch predictors
4
xx prediction
xx
  • The number of bits in an (m,n) predictor is
  • 2mn (number of prediction entries selected
    by the branch address)

2-bit global branch history
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