A BackEnd Design Flow for Single Chip Radios

1
Efficiency Enhancement Technique for RF CMOS
Power Amplifier Naratip Wongkomet and Prof.
Paul Gray University of California,
Berkeley BWRC Winter Retreat 12-13 January 2003
2
Existing Implementation

• Power amplifier (PA) is yet to be integrated
  with the
• rest of the transceiver

3
PA Design Challenges

• Power Amplifier design challenges
• Long talk time High efficiency
• High data rate High linearity

4
Power Amplifier Fundamentals
id
vin
VDD

RLoad
Ct
Lt
VT
vout
time
time
vin
Efficiency
vout
id
VDD
Class A
Class AB, C
Vout
Vout,max
time

• For good linearity, the transistor is biased
  such that it is always on. Poor
• efficiency. (Class A)
• For good efficiency, the transistor is biased
  such that it turns off during
• some parts of the cycle. Worse linearity.
  (Class AB,C)

5
Typical PA Operating Conditions

time

• PA output power usually is 15-20 dB below its
  peak power
• If the signal is amplitude modulated, its
  average power is lower than
• its peak power

6
Doherty Amplifier Concept

• Invented by W.H. Doherty in 1936
• Good power efficiency over a wide range of
• output power

Main Amplifier
Auxiliary Amplifier
Main on Aux. off
Main on Aux. on
Main on Aux. off
Main on Aux. on
?M
?max
?max
?A
Overall efficiency
Efficiency
0
0
Pout,max
Output power
Pout,max
Output power
7
Doherty Amplifier Block Diagram

Pout,max
Paux
Output power
Pmain
Pmain
0
Input power
Pin,max

• Use passive impedance inverter to efficiently
  combine the power from
• the main and auxiliary amplifiers

8
Doherty Amplifier Operation

I1
Vo
Vm
Zm Zo2/Zmo Zmo RL (1Ia/I1)
Zo 3RL
Im
Ia
RL
Dohertys efficiency
Vmax
?max
Imax
Vm
Ia
Vo
Imax/2
Vmax/3
Typical PAs efficiency
Im
Vin,max
0
Vin,max
0
Vin,max/3
Pout,max
Pout,max/9
0
Vin,max/3

• Auxiliary amplifier actively pulls the load
  impedance of the main amplifier

9
Doherty Amplifier Linearity

• Auxiliary amplifier ideally sees zero
  impedance
• Nonlinearities from the auxiliary amplifier
  can be absorbed into the
• impedance inverter network

• Auxiliary amplifier can be nonlinear
• Linearity of Main amplifier determines overall
  linearity

10
Impedance Inversion Network (1)

• In the original Doherty amplifier, a quarter
  wavelength transmission
• line is used
• Integrated lumped version is used in this
  project

jX
-jX
-jX
ZL
Zin X2/ZL
11
Impedance Inversion Network (2)
jX
RX/Q

-jX
-jX
Main
Aux.

• Low inductor Q causes this
• network to be lossy

Ploss/Pout
Normalized output power
12
Main Amplifier Design

• For good linearity, both transistors should
  not go
• into triode region.
• To get large output swing, Vdsat of both
  transistors
• must be small. This implies small
  gate-source
• voltage swing and large transistors width

13
Interstage Matching

• For good driving efficiency, use L to
• resonate out the input capacitance
• Output stage Cg is 28pF, which would need
• L0.25nH to resonate at 1.9 GHz.
• Use capacitive transformer interstage
• matching to lower the input capacitance
• at the expense of higher voltage swing

vg vin . k/(1k) Cin Cg . k/(1k)
14
Auxiliary Amplifier Design

Input drive (V)
Efficiency ()
VT
VT
Input DC bias voltage (V)
Input DC bias voltage (V)

• CMOS Class C amplifier has poor
  linearity-efficiency tradeoff
• Bias auxiliary amplifier in shallow class C
• Use the same schematic as the main amplifier

15
Simulation Results

• IS-95 input signal

Efficiency ()
ACPR (dB)
Normalized input
Normalized input

• The signal that is compatible with IS-95
  standard is used
• The maximum efficiency while still meeting the
  linearity requirements
• is 32 percent

16
Expected Research Contributions

• Demonstrate a highly integrated CMOS RF Power
  Amplifier
• with good efficiency and linearity
• Implement design techniques that help break
  the
• linearity-efficiency tradeoff barrier in the
  conventional
• PA design
• Develop prototype of CMOS Doherty amplifier

17
Status and Future Works

• Status
• Circuit-level design is completed
• Layout is currently underway
• Future works
• Complete the layout. The expected fabrication
  date is in Q1
• of year 2004.