Behavior Description 3

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Behavior Description 3

• Lecture 12

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Tasks (subroutines)
module bit_counter (data, count) input 70
data output 30 count reg 30 count
always _at_(data) t(data, count) task t
input 70 a output 30 c reg 30 c
reg 70 tmp begin c 0 tmp a
while (tmp) begin
c c tmp0 tmp tmp gtgt
1 end end endtask
endmodule
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Task Rules

• A task may be declared only within a module
• A task may be called only from a procedural
  statement
• A task may be called from the same module or from
  a different module by hierarchical de-referencing
• A task can call itself
• Variables may be defined locally within a task

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Functions
module word_aligner (w_in, w_out) input
70 w_in output 70 w_out assign
w_out align (w_in) function 70 align
input 70 word begin align
word if (align ! 0)
while (align7 0) align
align ltlt 1 end endfunction endmodule
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Timing Verification

• Static timing analysis
• Consider structure topology of circuit, enumerate
  signal propagation paths and determine if timing
  constraints are met
• Dynamic timing analysis
• Simulate circuit timing using input vectors
• Timing check tasks
• setup, hold, period, width, skew, recovery,
  nochange
• Can be invoked within a behavior or testbench or
  in a specify block

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Setup Constraint

• setup(data, posedge clock, 5)
• It specifies an interval before the active edge
  of clock.
• Data must arrive before the interval.

5
5
clock
data
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Hold Violation

• hold(data, posedge clock, 2)
• It specifies an interval after the active edge of
  clock.
• Data must be stable in the interval.

2
2
clock
data
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SetupHold

• setuphold(data, posedge clock, 5, 2)

2
2
5
5
clock
data
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Signal Period

• period(posedge clock, t_limit)
• Signal period must be sufficiently long.

clock cycle time
clock
t_limit
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Pulse Width

• width(posedge clock, t_mpw)
• The width of the clock pulse must not be too
  small.

clock pulse width
clock
t_mpw
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Clock Skew

• skew(negedge clk1, negedge clk2, t_skew)
• Signal skew is the arriving time difference of
  two signals.
• Clock skew should be limited.

clk1
skew
clk2
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Recovery Time

• recovery(negedge bus_control, bus_driver,
  t_rec)
• Time to go from Z to 0 or 1.

Bus_control
Bus_driver
Z
t_rec
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No Signal Change

• nochange(posedge clk, data, -5, 2)
• Equivalent to
• setuphold(data, posedge clk, 5, 2)

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Finite State Machines

• Explicit FSM
• States are defined explicitly
• FSM_style1 (page 240)
• Minimum behavioral description
• FSM_style2 (page 240
• Use behavioral to define next state, easier to
  use
• FSM_style3 (page 241)
• Output synchronized with clock

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Example 7.58 (page 242)