week12-1

1

• Lecture 30
• Scale and Yield
• Mar. 24, 2003

2
Scale

• In library

3
Yield of fabrication process

• 1. System Yield 0.95
•  2. Random Yield
•  A chip area
• D defective density
•  3. Total Yield

4
Example
5

• Lectures 31 and 32
• Routing and simulation
• Mar. 26,28, 2003

6
Topics

• Layouts for logic networks.
• Channel routing.
• Simulation.

7
Standard cell layout

• Layout made of small cells gates, flip-flops,
  etc.
• Cells are hand-designed.
• Assembly of cells is automatic
• cells arranged in rows
• wires routed between (and through) cells.

8
Standard cell structure
pin
VDD
n tub
pullups
Feedthrough area
Intra-cell wiring
p tub
pulldowns
VSS
pin
9
Standard cell design

• Pitch height of cell.
• All cells have same pitch, may have different
  widths.
• VDD, VSS connections are designed to run through
  cells.
• A feedthrough area may allow wires to be routed
  over the cell.

10
Single-row layout design
cell
cell
cell
cell
cell
Routing channel
cell
cell
cell
cell
cell
11
Routing channels

• Tracks form a grid for routing.
• Spacing between tracks is center-to-center
  distance between wires.
• Track spacing depends on wire layer used.
• Different layers are (generally) used for
  horizontal and vertical wires.
• Horizontal and vertical can be routed relatively
  independently.

12
Routing channel design

• Placement of cells determines placement of pins.
• Pin placement determines difficulty of routing
  problem.
• Density lower bound on number of horizontal
  tracks needed to route the channel.
• Maximum number of nets crossing from one end of
  channel to the other.

13
Pin placement and routing
a
b
c
a
b
c
b
c
a
b
c
a
before
before
14
Example full adder layout

• Two outputs sum, carry.

n1
x1
n4
n2
x2
sum
n3
carry
15
Layout methodology

• Generate candidates, evaluate area and speed.
• Can improve candidate without starting from
  scratch.
• To generate a candidate
• place gates in a row
• draw wires between gates and primary
  inputs/outputs
• measure channel density.

16
A candidate layout
17
Improvement strategies

• Swap pairs of gates.
• Doesnt help here.
• Exchange larger groups of cells.
• Swapping order of sum and carry groups doesnt
  help either.
• This seems to be the placement that gives the
  lowest channel density.
• Cell sizes are fixed, so channel height
  determines area.

18
Left-edge algorithm

• Basic channel routing algorithm.
• Assumes one horizontal segment per net.
• Sweep pins from left to right
• assign horizontal segment to lowest available
  track.

19
Example
A
B
B
C
A
B
C
20
Limitations of left-edge algorithm

• Some combinations of nets require more than one
  horizontal segment per net.

A
B
B
A
21
Vertical constraints

• Aligned pins form vertical constraints.
• Wire to lower pin must be on lower track wire to
  upper pin must be above lower pins wire.

A
B
B
A
22
Dogleg wire

• A dogleg wire has more than one horizontal
  segment.

A
B
B
A
23
Rats nest plot

• Can be used to judge placement before final
  routing.

24
Simulation

• Goals of simulation
• functional verification
• timing
• power consumption
• testability.

25
Types of simulation

• Circuit simulation
• analog voltages and currents.
• Timing simulation
• simple analog models to provide timing but not
  detailed waveforms.
• Switch simulation
• transistors as semi-ideal switches.

26
Types of simulation, contd.

• Gate simulation
• logic gates as primitive elements.
• Models for gate simulation
• zero delay
• unit delay
• variable delay.
• Fault simulation
• models fault propagation (more later).

27
Example switch simulation

c
0

d
X
X
o
b
X
a
1
c
0
28
Example, contd.

c
0

d
1
0
o
b
1
a
1
0
c
0
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