Architecture

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8086/8088 Architecture
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• Introduction
• CPU Architecture
• Execution Unit
• General Registers
• Arithmetic Logic Unit
• Flag Registers

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• Bus Interface Unit
• Instruction Queue
• Instruction Pointer
• Segment Registers

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8086 Architecture
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BIU
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BIU
Queue
CS
DS
seg
ES
SS
IP
BIU EU
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Control unit
AH
AL
AX
BH
BL
BX
CH
CL
CX
ALU
ALU
DH
DL
DX
SI
SI
EU
DI
DI
BP
BP
FLAG REG
SP
SP
FLAG
REG
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General Registers
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BIU AND EU

• The execution unit and the Bus Interface unit
  operate asynchronously.
• The EU waits for the instruction object code to
  be fetched from the memory by the BIU.
• The BIU fetches or pre-fetches the object code
  (16-bits at a time) and loads it into the six
  bytes queue.

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• EU fetches the instruction object code from the
  front of the instruction queue and executes the
  instruction in specified number of clock periods.
• The BIU is independent of the EU and attempts to
  keep the six-bytes queue filled with instruction
  object codes.
• If two or more of these six bytes are empty,
  then the BIU executes instruction fetch machine
  cycles as long as the EU does not have an active
  request for the bus access pending.

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EU
Request for data
Non sequential instruction
BIU
Fetched instruction discarded
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Arithmetic Logic Unit (ALU) ALU is 16-bits
wide. It can do the following 16-bits arithmetic
operations (i) Addition (ii)
Subtraction (iii) Multiplication
(iv) Division
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• Unsigned binary numbers
• Signed binary numbers (Integers)
• Unsigned packed decimal numbers
• Unsigned unpacked decimal numbers
• The ALU can also perform logical operations such
  as
• (i) NOT (iv) EXCLUSIVE OR
• (ii) AND (v) TEST
• (iii) OR

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Flag Register
C
AC
P
I
S
Z
O
D
T

• Condition Flags/ Status Flags
• Carry Flag (CF) - Set on high-order bit carry
  or borrow cleared otherwise
• Parity Flag (PF) - Ser if low-order 8 bits of
  result contain an even number of 1 bits cleared
  other wise.

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• Auxiliary Carry Flag (AC)
• Set on carry from or borrow to the low-order 4
  bits of AL cleared otherwise
• Zero Flag (Z)
• Set if result is zero cleared otherwise.
• Overflow Flag (O)
• Set if the signed result cannot be expressed
  within the number of bits in the destination
  operand cleared otherwise.
• Sign flag (S)
• Set equal to high-order bit of result

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• Control Flags
• Trap flag (T) Once set, a single-step interrupt
  occurs after the next instruction executes TF is
  cleared by the single-step interrupt.
• Interrupt Flag (I) When set, maskable interrupts
  will cause the CPU to transfer control to an
  interrupt vector-specified location.

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• Direction Flag (D) Causes string instructions
  to auto- decrement the appropriate index register
  when set clearing DF causes auto increment.

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Bus Interface Unit (BIU)

• An instruction queue
• An Instruction pointer
• Segment registers

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An instruction queue

• First-in-first-out
• EU when ready fetches next instruction from
  the queue.
• BIU fetches as many as 6 instruction bytes
• Speeds up program execution.

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Instruction Pointer

• It is 16 bits.
• It contains 16 bits address pointing to the next
  instruction that has to be fetched.
• It always adds with the displaced 16 bits code
  segment register to fetch the opcode from memory.

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Segment Register

• Four Segment registers
• Code Segment register
• Data Segment register
• Stack Segment register
• Extra Segment register
• They are 16 bits wide

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Segmented Memory

• There are two types of memory organization.
• Linear addressing
• The entire memory space is available to the
  processor in one linear array.
• 2. Segmented addressing
• Divides the available memory space into chunks
  called segments.

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• The processor is limited to
  accessing program instructions and
  data from the active segments only.
• Within the 1 MB of memory space the 8086 defines
  four 64K bytes memory blocks called
• Code segment (Instruction code)
• Stack segment (Int., Subrout. return address)
• Data segment (data for the program)
• Extra segment (shared data)

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Segment Register
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• Code Segment
• Points to Instruction operation code
• The effective address is always from the
  Instruction Pointer (IP).

• Data Segment / Extra Segment
• Points to data
• The effective address may be from -

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• Direct
• Register Indirect BX, SI, DI, BP
• Indexed SI Data, DI data
• Base BX Data,
• BP data
• Base Indexed
• SI BX,
• DI BX,
• SI BP,
• DI BP

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Base Indexed Relative SI BX Data, DI
BX Data, SI BP Data, DI BP
Data
Stack Segment SP register BP register
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• Advantages of Segmentation
• Separate code and data area. One set of code can
  work on different sets of data.
• 2. Programs can be relocatable. It means the
  programs can run at any location in memory.

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• Disadvantages of Segmentation
• Segmentation seems confusing.
• Segmented memory introduces extra complexity in
  both hardware and software.
• It limits segments to 64K bytes

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• Given that the EA of a datum is 2359 H and the DS
  490B H, what is the physical address of the
  datum?
• DS 490B0 H
• EA 2359 H
• Physical add. 4B409 H
• 2. If a physical branch address is 5A230 H when
  (CS) 5200 H, what will be the branch address if
  the (CS) is changed to 7800 H.

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Given CS 5200 To find
Offset XXXX Given Physical
add. 5A2 3 0 H Hence Offset Physical add
- (Segment address displaced by 4-bits)
Offset 5A230 - 52000 8230 H If the CS is
changed to 7800 H the Physical address will be
78000 8230 80230
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• Briefly describe 8086 microprocessor's
  architecture.
• Describe the function of the 8086 queue.
• How does the queue speed up process operation?
• Assuming CS 7040H, what is the physical
  address if instruction pointer contains 539CH?

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5. What physical address is represented by
(a) 4370561E (b) 7A320028 6. . What is
the advantage of using a CPU register for
temporary data storage over using a memory
location? 7. If the stack segment register
contains 3000H and the stack pointer register
contains 8434H, what is the physical address of
the top of the stack?
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• 8. Describe the function of 8086 with respect to
  (i) Queue (ii) Flag register (iii) Segment
  register (iv) Arithmetic Logic unit (v)
  General Registers (vi) BIU and EU
• 9. Discuss how physical address is generated?
• What is the purpose of the IP register?
• What conditions will cause the BIU to suspend
  fetching instructions?

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• 12. What is the purpose of the segment register
  in the operation of the microprocessor?
• What is the purpose of the direction flag?
• Can Data Segment be used to access stack?
• Can all the segment registers be used to get
  data?