FPCCD Vertex detector

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FPCCD Vertex detector

• 22 Dec. 2006
• Y. Sugimoto
• KEK

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Vertex detector for ILC

• Performance goal
• Impact parameter resolution
• sIP 5 ? 10/(pb sin3/2q ) mm ( ltlt ct of D,
  t )

Track density (/cm2/BX)

• This m.s. term is very challenging
• Very thin wafer, beam pipe, support
• Innermost layer as close to IP
• as possible ? High b.g. rate
• ? High pixel occupancy

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Vertex detector options

• If signals of one train (2820 bunches) are
  accumulated, too many hits by beam b.g. ? for 25
  mm pixels, the pixel occupancy gt10 for B3T and
  R20mm
• Solutions
• Fast readout Example Column Parallel CCD
  _at_50MHz, 20 frames/train
• No time to wait for diffusion in epi-layer after
  particle incident
• ? Fully depleted CCD ? No diffusion ?Poor
  resolution
• Still smaller pixel size is necessary to recover
  the resolution
• Possible effect by RF noise by beam
• Analog registers in each pixel (20/pixel), and
  readout between trains
• CMOS Flexible Active Pixel Sensor (FAPS)
• CCD In-situ Storage Image Sensor (ISIS)
• Fine and complicated structure ? Large area OK?
• Make pixel density x20?Fine Pixel CCD (FPCCD)

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Vertex detector options
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GLD Vertex detector

• FPCCD vertex detector as the baseline design of
  GLD
• Accumulate hit signals for one train (2840 BX)
  and read out between trains (200ms) ? Completely
  free from EMI
• Fine pixel of 5mm (x20 more pixels than
  standard pixels) to keep low pixel occupancy ?
  Spatial resolution of 1.5mm even with digital
  readout
• Fully depleted epitaxial layer to minimize the
  number of hit pixels due to charge spread by
  diffusion
• Two layers in proximity make a doublet (super
  layer) to minimize the wrong-tracking probability
  due to multiple scattering
• Three doublets (6 CCD layers) make the detector
• Tracking capability with single layer using hit
  cluster shape can help background rejection
• Multi-port readout with moderate (20MHz) speed
  (Very fast readout (gt50MHz) not necessary)
• Simpler structure than FAPS or ISIS ? Large area
• No heat source in the image area

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• B.G. rejection by hit cluster shape
• (tracking capability with single layer!)

• Standard CCD

• Fine Pixel CCD

High Pt Signal
Low Pt b.g.
Z f















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Challenge of FPCCD

• Fully depleted
• Lorentz angle
• tanqrHmB, rH Hall coefficient1, m
  mobility (m2/Vs), B Magnetic field (T)
• Stronger E-field in dep. layer (gt104V/cm 1V/mm)
  gives saturation of carrier velocity and smaller
  m
• ? Epi layer of 15mm would be OK
• Radiation tolerance
• Small pixel (5 mm)
• Fast readout speed(20Mpix/s)
• Multi-port readout
• H-Register in image area
• Low noise
• lt50 e (total) ? lt 30 e (CCD)

• Low power consumption
• Metal layer
• Low drive pulse voltage
• Output circuit
• Large area10x65mm2(in)/20x100mm2(out)
• Thinning(lt50 mm)
• Full well capacity
• gt104 e is OK
• Readout ASIC
• Necessary for proto-type ladder

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Lorentz angle

• tanqrHmBmB (mm2/Vs, BT), mv/E

m0.07 m2/Vs
m0.1 m2/Vs
m0.14 m2/Vs
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RD for FPCCD

• Study of fully depleted CCD
• Charge spread
• Lorentz angle
• Radiation damage
• Development of FPCCD
• 3 rounds expected
• Prototype ladder in 5 years
• Collaboration with Hamamatsu
• Minimization of material budget
• Wafer thinning
• FEA study of support structure
• Development of readout ASIC

Supported by Gakujyutu Sousei
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RD Roadmap
2006
2007
2008
2009
2010
ILC Project (Detector)
DCR
DOD
LOI
Construction
Study of fully Depleted CCD
2nd round
3rd round (prototype ladder)
Design of small Prototype of FPCCD
FPCCD fabrication
Sample test
Sample test
Sample test
Development of readout ASIC for prototype CCD
FPCCD VTX
Wafer thinning and the support structure
Other 2nd priority RDs
DOD Detector Outline Document DCR Detector
Concept Report LOI Letter of Intent (?)
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Short term plan

• Study of fully depleted CCD
• New CCDs will be delivered mid December
• Epi-layer 30mm / 15mm
• Pixel size 24mm
• Study of charge spread and Lorentz angle
• Using green YAG LASER
• B-field up to 1T
• Radiation tolerance
• Electron / neutron damage
• Dark current / charge transfer inefficiency
• Study of support structure
• FEA study of Si-RVC-Si sandwich structure (RVC
  Reticulated Vitreous Carbon)

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Study of charge spread

• Apparatus

CCD for test (Back-illumination)
CCD for reference (Front-illumination)
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Charge spread

• Front illumination
• Standard

• Back illumination
• Deep2

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Field simulation
NA1.0, 1.5, 2.0, 2.5, 3.0, 3.5, 4.0
x1013/cm3
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Summary

• We have started RD of FPCCD for GLD vertex
  detector
• Study of fully depleted CCD is on going in
  FY2006, and will be continued to FY2007
• The 1st test sample of FPCCD is expected to be
  made by Hamamatsu in FY2007
• We wish to construct and test prototype ladders
  of FPCCD by the end of Gakujyutu-Sousei project,
  but the budget (for r.o. ASIC and support
  structure) is not enough to complete that goal