Two, Four, Six, Eight

1
Two, Four, Six, Eight.What is our Trigger Rate

• Collaboration Meeting March 2003

2
Roadmap

• The trigger group has been studying the
  performance of various trigger
• subsystems for different numbers of interactions
  per beam crossing (ints/BCO),
• in anticipation of possible questions from P5,
  and I will summarize the results
• L1 pixel trigger
• Results from the BTeV Proposal (May 2000)
• FPGA segment tracker
• DSP timing results
• L1 muon trigger
• L2 trigger
• Summary table

3
Level 1 hardware
The BTeV Pixel Trigger System
Switch
DSP Farm
FPGASegment Tracker
4
Level 1 hardware (cont.)
FPGA Hardware Studies (buffer needs timing)
5
How to speed up L1 code

• As described in Btev Proposal update Much of L1
  algorithm optimization
• work has focused on the segment matching
  routine.Thecurrent version is
• 8x faster than original

• However, as the previous slide shows, gt50 of
  total L1 processing time is
• still taken up by the segment matching

• HASH SORTER Simple and novel hardware solution
  (Jin-Yuan Wu)

- sort inner and outer triplets into bins of
slope (non-bend view)
- attempt to match only inner/outer triplets
with similar slope
- will significantly reduce number of
combinations that need to be tried
- no physics cuts applied in hardware,
simply sorting triplets into bins
NEXT SLIDE test hash sorter idea with C-code
implementation
6
Test hash sorter idea
1.5-2x faster
4-5x faster
7
Hash sorter Q A

• Can this be implemented in hardware?

- YES !
- In fact, we have finished the design for a
Xilinx FPGA, and successfully compiled it
yesterday

• What changes need to be done to existing
  pre-prototype hardware?

- NONE !
- The firmware will fit comfortably in Buffer
Manager FPGA of the existing pre-prototype
board
- Hash sorter takes up 10 of Buffer Manager
FPGA, while current Buffer Manager FPGA
utilization only 40
8
Trigger Summary
Current trigger results