Power supply and substrate noise analysis Reference tool experience with silicon validation

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Power supply and substrate noise analysis
Reference tool experience with silicon validation
Yoji Bando14, Daisuke Kosaka4, Goichi
Yokomizo2, Kunihiko Tsuboi2, Ying Shiun Li3,
Shen Lin3, Makoto Nagata14 Kobe University1,
STARC2, Apache Design Solutions, Inc.3,
A-R-Tec Corp.4
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Motivation

• Power supply (PS) noise impacts on circuits -
  digital timing variation, leakage increase -
  analog-MS substrate crosstalk, substrate
  coupling
• Digital PS integrity technology, with
  enhancements of substrate coupling/noise
  analysis
• On-chip measurements connect EDA analysis with
  reality

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Technical contribution

• Multi-party collaboration for validated noise
  analysis Chip designer, IP provider, EDA tool
  provider
• Fully integrated power and substrate noise
  analysis A high capacity solver for a single
  large matrix unifying on-chip power grids and
  current sources, chip-level substrate meshes,
  and off-chip board networks
• On-chip noise measurements for silicon
  correlation Noise monitors with very many
  probing channels for thorough correlation of
  simulation and measurements

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Multi-party collaboration for confidence noise
analysis
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Key technology contributions 1
PSA and SNA
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Key technology contributions 2
Power library Logic cell characterization
Integrated PS andsubstrate noise simulation
Simulation and Silicon correlation
Verification planningand test chip design
On-chip noisemeasurements
Physical design and sign-off flow
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Noise evaluation chip overview
Substrate noise probe array in left top area
5.0 mm
Substrate noise probe arrayin right btm. area
PS noise probe array for 32-bit mP

• A 32-bit processor (SH-4) with 210 kB memory
  capacity
• Densely distributed on-chip dynamic noise
  monitors
• 90-nm CMOS, 5LM, 1.0 V technology

SH-4 Renesas technology
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Noise probing locations in mP core
2.5 mm
32-bit uP core
2.0 mm
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Noise probing locations on substrate
Substrate noise evaluation area (120 probing
points in total)
P GR(guard ring)
deep NwellGR
deep Nwellpocket
1.6 mm
0.5 mm
P probing points
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On-chip noise monitor circuitry
PS noiseprobing array
Substrate (P) noise probing array
Off-chip
On-chip
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PS noise waveform measurements
Probing _at_SH-4 center, Fclk 50 MHz
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PS noise intensity code dependence
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Unified matrix of chip-level noise analysis
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Full chip PS and substrate noise analysis flow
overview
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Noise source modeling
Standard cell library (LEF/DEF)
Apache Power Library (APL) - SPICE simulation
I(t) LUT for in/out condition, load caps -
Post-layout extraction logic cell level
Cesc, Resr
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Substrate network modeling
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Off-chip network modeling
Off-chip power delivery network (PDN)- FR4
board, package, bonding wires macroscopically
seen by a chip - Lumped LCR extraction between
Vdd and Gnd terminals- Considerable impacts on
noise components from DC to a few 100 MHz
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Unified matrix for quality noise analysis
Substrate coupling analysis enhances accuracy of
noise analysis in digital as well as mixed-signal
circuits.
Ground noise in SH-4 processor _at_ 50 MHz,
comparing simulation with on-chip measurements
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Dynamic PS noise waveforms
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Gnd/Psub noise chip-wide Vpp map
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Substrate noise (Vpp) trend yL axis
Fck 50 MHz
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Substrate noise (Vpp) trend xL axis
Fck 50 MHz
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Cost of Simulation
SH-4 core 670k gates, SRAM cells 11.2M trs.,
of I/O 208 pins, chip area 5.0 mm x 5.0 mm 750
k extraction 1.0 h, simulation 1.5 h (for 120
nsec) extraction 6.6 GB, simulation 3.5 GB 2-core
Opteron x 2 _at_ 2.8GHz, 64 GB memory
Chip to simulate Mesh size CPU time Memory
usage Machine spec.
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Summary

• Unification of on-chip power grids, substrate,
  and off-chip network realizes dynamic PS and
  substrate noise simulation with high accuracy
• Comprehensive on-chip noise measurements
  establish reference experience of silicon
  validation
• Close correlation of simulation and
  measurements achieves designers confidence of
  noise analysis