15-213 Recitation 6 Greg Reshko

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15-213 Recitation 6Greg Reshko

• Office Hours Wed 200-300PM
• March 10th, 2003

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Outline

• Exam 1
• Cache
• Quick Review
• Detailed Examples

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Exam 1

• Regrades are done
• Any questions?

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Review Addressing
Address A
b bits
t bits
s bits
0
m-1
lttaggt
ltset indexgt
ltline offsetgt
  
B1
1
0
v
tag
  
set s
  
B1
1
0
v
tag

• Address A is in the cache if its tag matches one
  of the valid lines in the set associated with the
  set index of A

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Review Parameters

• B 2b line size
• E associativity
• S 2s number of sets
• Cache size B E S
• s set index
• b byte offset
• t tag
• m address size
• t s b m

Cache Parameters
Address A
b bits
t bits
s bits
0
m-1
Line Parameters
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Simple example cache parameters

• 8 KB direct-map cache with 64 byte lines
• word size is 32 bits
• A direct-map cache has an associativity of 1
• Determine t, s, and b
• B 2b 64, so b 6
• B E S C 8192 (8 KB), and we know E 1
• S 2s C / B 128, so s 7
• t m s b 32 6 7 19, so t 19

t 19
s 7
b 6
0
31
5
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Direct-Mapped Cache

• Three steps to extract data from cache
• Set Selection
• Use set index bits.
• Line Matching
• Easy, since one line per set.
• Word Selection
• Use block offset bits.
• What this means should be clear in a moment

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Set V Tag Byte 0 Byte 1
0 (00) 0
1 (01) 0
2 (10) 0
3 (11) 0
Initially empty cache
Address A
b bits
t bits
s bits
0
m-1
Cache Parameters S4, i.e. 4 sets E1, i.e. 1
line per set B2, i.e. 2 bytes per block m4,
i.e. 4-bit addresses
S22 gt s2 B21 gt b1 tm-s-b4-2-11 gt t1
Determine cache parameters first
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Set V Tag Byte 0 Byte 1
0 (00) 1 0 m0 m1
1 (01) 0
2 (10) 0
3 (11) 0
Read word at address 0
Address A
b bits
t bits
s bits
0
00
0
0
m-1
Address is 0 0 0 00 0 Therefore Tag
0 Set 00 Block 0 This is a cache miss, since
V for this set is 0. Fetch m0 AND m1 and
store it.
Address Tag/Set/Block Cache Location
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Set V Tag Byte 0 Byte 1
0 (00) 1 0 m0 m1
1 (01) 0
2 (10) 0
3 (11) 0
Read word at address 1
Address A
b bits
t bits
s bits
1
00
0
0
m-1
Address is 1 0 0 00 1 Therefore Tag
0 Set 00 Block 1 This is a cache hit, since
V for this set is 1. Nothing changes.
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Set V Tag Byte 0 Byte 1
0 (00) 1 0 m0 m1
1 (01) 0
2 (10) 1 1 m12 m13
3 (11) 0
Read word at address 13
Address A
b bits
t bits
s bits
1
10
1
0
m-1
Address is 13 0 1 10 1 Therefore Tag
1 Set 10 Block 1 This is a cache miss, since
V for this set is 0. Fetch m12 and m13 and
store it.
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Set V Tag Byte 0 Byte 1
0 (00) 1 1 m8 m9
1 (01) 0
2 (10) 1 1 m12 m13
3 (11) 0
Read word at address 8
Address A
b bits
t bits
s bits
0
00
1
0
m-1
Address is 8 0 1 00 0 Therefore Tag
1 Set 00 Block 0 This is a cache miss, since
V for this set is 0. Since m8 maps to the same
place as m0, we will overwrite m0 (i.e.
eviction). Fetch m8 and m9 and store it.
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Set V Tag Byte 0 Byte 1
0 (00) 1 0 m0 m1
1 (01) 0
2 (10) 1 1 m12 m13
3 (11) 0
Read word at address 0
Address A
b bits
t bits
s bits
0
00
0
0
m-1
Address is 0 0 0 00 0 Therefore Tag
0 Set 00 Block 0 This is a cache miss, since
tags do not match. Since m0 maps to the same
place as m8, we will overwrite m8. But we
just stored m0 there! This is called
thrashing. Fetch m0 and m1 and store it.
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Set Associative Cache

• Three steps to extract data from cache
• Set Selection
• Same as direct-mapped. Use set index bits.
• Line Matching
• Check tag and valid bits for all lines in the
  set.
• Word Selection
• Same as direct-mapped. Use block offset bits.
• What this means should be clear in a moment

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1. Set Selection
Address A
b bits
t bits
s bits
m-1
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2. Line Matching
Address A
b bits
t bits
s bits
m-1
  
B1
1
0
valid
tag
Valid or not?
  
set 0
  
B1
1
0
valid
tag
To access a location, tags must match and the
entry must be valid
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3. Word Selection
Address A
b bits
t bits
s bits
m-1
  
B1
1
0
valid
tag
  
set 0
  
B1
1
0
valid
tag
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How to actually access it?

• Same idea
• Convert Address to ltTag/Set/Blockgt
• Convert ltTag/Set/Blockgt to Cache Location

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Fully Associative Cache

• Three steps to extract data from cache
• Set Selection
• There is only one set and hence no set bits.
• Line Matching
• Same as in set associative cache, except that
  there are many more lines per set now.
• Word Selection
• Same as in set associative cache.
• What this means should hopefully be clear by now.

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Conclusion

• Good caching faster code
• Spatial locality (same address many times)
• Temporal Locality (nearby locations)
• Blocking (split one chunk into little pieces)
• Etc