General Iterative Heuristics for VLSI Multiobjective Partitioning

1
General Iterative Heuristics for VLSI
Multiobjective Partitioning

• by
• Dr. Sadiq M. Sait
• Dr. Aiman El-Maleh
• Mr. Raslan Al Abaji
• King Fahd University
• Computer Engineering Department

2
Outline .

• Introduction
• Problem Formulation
• Cost Functions
• Proposed Approaches
• Experimental results
• Conclusion

3
VLSI Technology Trend
7.5M333MHz0.25um
Design Characteristics
3.3M200MHz0.6um
1.2M50MHz0.8um
0.13M12MHz1.5um
0.06M2MHz6um
Cycle-basedsimulation,FormalVerification
Top-DownDesign,Emulation
HDLs, Synthesis
CAESystems, Siliconcompilation
Key CAD Capabilities
SPICE Simulation
The Challenges to sustain such an exponential
growth to achieve gigascale integration have
shifted in a large degree, from the process of
manufacturing technologies to the design
technology.
4
The VLSI Chip in 2006

Technology 0.1 um Transistors 200 M Logic
gates 40 M Size 520 mm2 Clock 2 - 3.5 GHz Chip
I/Os 4,000 Wiring levels 7 - 8 Voltage 0.9 -
1.2 Power 160 Watts Supply current 160 Amps
Performance Power consumption Noise
immunity Area Cost Time-to-market Tradeoffs!!!
5
VLSI Design Cycle

• VLSI design process is carried out at a number of
  levels.

• System Specification
• Functional Design
• Logic Design
• Circuit Design
• Physical Design
• Design Verification
• Fabrication
• Packaging Testing and Debugging

6
Physical Design
The physical design cycle consists of

• Partitioning
• Floorplanning and Placement
• Routing
• Compaction

Physical Design converts a circuit description
into a geometric description. This description is
used to manufacture a chip.
7
Why we need Partitioning ?

• Decomposition of a complex system into smaller
  subsystems.
• Each subsystem can be designed independently
  speeding up the design process (divide-and
  conquer-approach).
• Decompose a complex IC into a number of
  functional blocks, each of them designed by one
  or a team of engineers.
• Decomposition scheme has to minimize the
  interconnections between subsystems.

8
Levels of Partitioning
System
System Level Partitioning
PCBs
Board Level Partitioning
Chips
Chip Level Partitioning
Subcircuits / Blocks
9
Motivation

• Need for Power optimization
• Portable devices.
• Power consumption is a hindrance in further
  integration.
• Increasing clock frequency.
• Need for delay optimization
• In current sub micron design wire delay tend to
  dominate gate delay. Larger die size imply long
  on-chip global routes, which affect performance.
• Optimizing delay due to off-chip capacitance.

10
Objective

• Design a class of iterative algorithms for VLSI
  multi objective partitioning.
• Explore partitioning from a wider angle and
  consider circuit delay , power dissipation and
  interconnect in the same time, under balance
  constraint.

11
Problem formulation

• Objectives
• Power cost is optimized AND
• Delay cost is optimized AND
• Cutset cost is optimized
• Constraint
• Balanced partitions to a certain tolerance
  degree. (10)

12
Cutset

• Based on hypergraph model H (V, E)
• Cost 1 c(e) 1 if e spans more than 1 block
• Cutset sum of hyperedge costs
• Efficient gain computation and update

13
Delay Model

• path ? SE1 ? C1?C4?C5?SE2.
• Delay? CDSE1 CDC1 CDC4 CDC5 CDSE2
• CDC1 BDC1 LFC1 ( Coffchip CINPC2 CINPC3
  CINPC4)

14
Delay
Delay(Pi)
Delay(Pi)
Pi is any path Between 2 cells or nodes P
set of all paths of the circuit.
15
Power
The average dynamic power consumed by CMOS logic
gate in a synchronous circuit is given by
Ni is the number of output gate transition per
cycle( switching Probability)
Is the Load Capacitance
16
Power
Load Capacitances driven by a cell before
Partitioning
additional Load due to off chip capacitance.(
cut net)
Total Power dissipation of a Circuit
17
Power
Can be assumed identical for all nets
Set of Visible gates Driving a load outside the
partition.
18
Balance
The Balance as constraint is expressed as
follows
However balance as a constraint is not appealing
because it may prohibits lots of good moves.
Objective Cells(block1) Cells( block2)
19
Fuzzy logic for cost function

• Imprecise values of the objectives
• best represented by linguistic terms that are
  basis of fuzzy algebra
• Conflicting objectives
• Operators for aggregating function

20
Use of fuzzy logic for Multi-objective cost
function

• The cost to membership mapping.
• Linguistic fuzzy rule for combining the
  membership values in an aggregating function.
• Translation of the linguistic rule in form of
  appropriate fuzzy operators.

21
Some fuzzy operators

• And-like operators
• Min operator ? min (?1, ?2)
• And-like OWA
• ? ? min (?1, ?2) ½ (1- ?) (?1 ?2)
• Or-like operators
• Max operator ? max (?1, ?2)
• Or-like OWA
• ? ? max (?1, ?2) ½ (1- ?) (?1 ?2)
• Where ? is a constant in range 0,1

22
Membership functions
Where Oi and Ci are lower bound and actual cost
of objective i ? i(x) is the membership of
solution x in set good i gi is the relative
acceptance limit for each objective.
23
Fuzzy linguistic rule

• A good partitioning can be described by the
  following fuzzy rule
• IF solution has
• small cutset AND
• low power AND
• short delay AND
• good Balance.
• THEN it is a good solution

24
Fuzzy cost function
The above rule is translated to AND-like OWA
Represent the total Fuzzy fitness of the
solution, our aim is to Maximize this fitness.
Respectively (Cutset, Power, Delay , Balance )
Fitness.
25
GA for multiobjective Partitioning
Algorithm (Genetic_Algorithm) Construct_Population
(Np) For j 1 to Np Evaluate_Fitness
(Populationj) End For For i 1 to Ng
For j 1 to No (x,y) ?
Choose_parents offspringj ? Crossover(x,y)
EndFor Population ? Select ( Population,
offspring, Np ) For k 1 to Np Apply
Mutation (Populationk) EndFor EndFor
26
Solution representation
27
GA implementation

• Different population sizes
• Parent selection Roulette wheel
• The probability of selecting a chromosome for
  crossover is
• Np is the population size

28
GA implementation

• Simple single point
• crossover

• Selection before mutation
• Roulette wheel (rlt)
• Elitism random (ernd)

29
Tabu Search

• Algorithm Tabu_Search
•  Start with an initial feasible solution S ? ?
• Initialize tabu list and aspiration level
• For fixed number of iterations Do
• Generate neighbor solutions V ? N(S)
• Find best S ? V
• If move S to S is not in T Then
• Accept move and update best solution
• Update T and AL
• Else If Cost(S) lt AL Then
• Accept move and update best solution
• Update T and AL
• End If
• End For

30
TS implementation

• Neighbor solution
• Change the block of a randomly selected cells.
• The Tabu list size depends on the circuit size.

31
TS implementation

• Tabu list
• Store index of one of the swapped cell.
• Various sizes for tabu list.
• Aspiration Level
• The best neighbor is better than the global best.
  

32
Experimental Results
ISCAS 85-89 Benchmark Circuits
33
GA Vs Tabu Multi-objective
34
Circuit S13207 GA
35
Circuit S13207 TS
36
Circuit S13207 GA Vs TS time
37
Conclusion

• The present work successfully addressed the
  important issue of reducing power and delay
  consumption in VLSI circuits.
• The present work successfully formulate and
  provide solutions to the problem of
  multiobjective VLSI partitioning
• TS partitioning algorithm outperformed GA in
  terms of quality of solution and execution time

38
Thank you.