Synchronous%20Digital%20Design%20Methodology%20and%20Guidelines

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Synchronous Digital Design Methodology and
Guidelines

• Digital System Design

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What is Synchronous Design and Why?

• Rules
• All flip-flops clocked by one common clock
• Reset only used for initialization
• Advantages
• Races and hazards are no problem
• Simple design methodology
• Wide EDA tool support
• Simple DFT

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Timing Hazard

• Static hazard possibility of a brief signal
  value change when the signal was expected to be
  stable, due to timing (glitch)
• Dynamic hazard possibility of multiple output
  transitions caused by a single input transition
  due to multiple signal paths with different delays

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Static Hazard
If d is the delay of each gate
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Analyzing Static Hazards using Karnaugh maps
A static hazard can occur when changing a single
input variable causes a jump from one prime
implicant to another Solution include an
additional prime implicant
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Eliminating hazards using Flip-Flops
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Synchronous Design

• Three things must be ensured by the designer
• Minimize and determine clock skew
• Account for flip-flop setup and hold times
• Reliably synchronize asynchronous inputs

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Timing Analysis
gt0 Setup time margin
gt0 Hold time margin
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Example

• The circuit of Figure 1 is synthesized to a
  gate-level netlist. What is the estimated maximum
  operating frequency for the circuit, assuming
• A flip-flop setup-time requirement of 0.8 ns,
• A flip-flop hold-time requirement of 0.2 ns,
• A flip-flop propagation delay of 1 ns,
• A comb1 (combinational) block delay of 6 ns
• A comb2 block delay of 10 ns
• A comb3 block delay of 5 ns
• A comb4 block delay of 4 ns
• A comb5 block delay of 2 ns

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Clock skew
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Example

• Determine the maximum frequency of the following
  circuit with and without skew

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Clock Jitter
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Clock Gating

• Clock gating is done to disable the clock for low
  power consumption using a clken signal
• It is wrong to gate the clock in the following
  way, instead use a synchronous load (enable)
  signal

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Asynchronous Inputs
It is impossible to guarantee setup and hold
timing constraints on inputs synchronized with a
clock unrelated to the system clock
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Asynchronous inputs

• Synchronize only in one place

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Metastability

• Metastability is a phenomenon that may occur if
  the setup and hold time requirements of the FF
  are not met, leading in the output settling in an
  unknown value after unspecified time.

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Reliable synchronizer design
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Example

• Design a synchronizer that synchronizes two
  inputs async1 and async2 generated with a 50 MHz
  clock CLK1, to a system with a 33 MHz clock CLK2
  totally independent of CLK1. Draw appropriate
  timing diagrams.

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Mean-time between failures
f frequency of flip-flop clock a number of
asynchronous input changes per second in
flip-flop input To, t constants depending on
flip-flop electrical characteristics Assume a 10
Mhz clock, ts 20 ns, To 0.4 sec, t 1.5 ns
and that the asynchronous input can change
100,000 times per second, then tr 1/f ts 80
ns MTBF(80ns) exp(80/1.5)/0.4107105
3.61011 s
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Cascaded synchronizer
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Synchronizing bus transfers

• Do not use dual f/f synchronizers in all bits,
  this will only increase the chances of
  metastability
• Synchronize the control signals and read the
  input when safe to do so

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Synchronization circuit
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Synchronizing high-speed data transfers

• What happens when the asynchronous inputs are
  clocked faster than the system clock? Or in a
  long burst transfer such as AXI bus?

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FIFO Synchronizer basic concept

• On burst transfers, the receiver cannot afford to
  wait for the signal to settle.
• Solution A dual-port RAM FIFO
• Problem How do we synchronize the counters?

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Summary

• In order to avoid hazards and races, synchronous
  design is used
• In synchronous design a single common clock is
  used and reset is only used for initialization
• The only considerations in synchronous design are
  the flip-flop setup and hold times, clock skew
  and asynchronous input synchronization
• Asynchronous inputs are commonly synchronized
  using 2 flip-flops clocked with the synchronous
  system clock
• Synchronization should only be done in one place
• In bus transfers, synchronize only the control
  signals or use a FIFO