Synchronous%20Digital%20Design%20Methodology%20and%20Guidelines

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Synchronous Digital Design Methodology and
Guidelines

• Digital System Design

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Synchronous Design

• All flip-flops clocked by one common clock
• Reset only used for initialization
• Races and hazards are no problem

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Synchronous Design

• Three things must be ensured by the designer
• Minimize and determine clock skew
• Account for flip-flop setup and hold times
• Reliably synchronize asynchronous inputs

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Timing Analysis
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Clock skew
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Example

• Determine the maximum frequency of the following
  circuit with and without skew

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Clock Jitter
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Clock Gating

• Clock gating is done to disable the clock for low
  power consumption using a clken signal
• It is wrong to gate the clock in the following
  way, instead use a synchronous load (enable)
  signal

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Asynchronous Inputs
It is impossible to guarantee setup and hold
timing constraints on inputs synchronized with a
clock unrelated to the system clock
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Asynchronous inputs

• Synchronize only in one place

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Metastability

• Metastability is a phenomenon that may occur if
  the setup and hold time requirements of the FF
  are not met, leading in the output settling in an
  unknown value after unspecified time.

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MTBF
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Reliable synchronizer design
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Multi-cycle synchronizer
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Example

• Design a synchronizer that synchronizes two
  inputs async1 and async2 generated with a 50 MHz
  clock CLK1, to a system with a 33 MHz clock CLK2
  totally independent of CLK1. Draw appropriate
  timing diagrams.

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Multi-cycle synchronizer with deskewing
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Cascaded synchronizer
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Example

• Design a digital synchronizer to capture valid
  data according to the following timing diagram

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Solution
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Synchronizing high-speed data transfers

• What happens when the asynchronous inputs are
  clocked faster than the system clock?

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Case study Ethernet receiver
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Byte holding register
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SCTRL circuit
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Testing Basics
Defect A difference between intended design and
actual hardware Error A wrong output produced
through a defect Fault A defect in a higher
abstraction level
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Example
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Controllability and observability

• Controllability The difficulty of setting a
  specific signal to 0 or 1
• Observability The difficulty of reading a
  specific signal
• Electron beam testing is too expensive
• Must set signal through primary inputs and
  observe through primary outputs

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Design For Testability (DFT)
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Boundary scan

• In boundary scan, all flip-flops enter a test
  mode where they are controllable and observable
• After functional verification, normal flip-flops
  are replaced by scan flip-flops
• Only D flip-flops must be used
• Clocks must not be generated internally

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Built-In Self-Test (BIST)