The IC Implementation Tool Set

1
The IC ImplementationTool Set

• Gary Smith
• Chief Analyst EDA
• Gartner Dataquest

2
The Move to the IC Implementation Tool Set

• The Driver - The move to .13 to .10 micron
  designs.
• The Status - Close but no cigar.
• What happens if the IC Implementation Tool Set is
  never completed ?
• What about custom ?
• The next challenge.

3
The IC Implementation Tool Set
The Darringer Door
4
The Status - Close but no cigar. Synopsys
The Darringer Door
5
The Status - Close but no cigar. Cadence
But ! - Only one Design completed.
The Darringer Door
6
The Status - Close but no cigar. Magma
But ! - 2 Million gates max ? - 200 MHz max ?
- DFT ? - A Core/Block tool ?
7
The Status - Close but no cigar. Avant!
Monterey
No synthesis No cigar
The Darringer Door
8
The IC Implementation Tool SetTodays Flow
Silicon Perspective
Synopsys
Avant!
9
What Happens if the IC Implementation Tool Set is
Never Completed ?
Silicon Virtual Prototype
Physical Synthesis
A P I ? ? ?
DFT
Timing Power Analysis
IC Place Route
10
What about Custom ?

• Limits the ability to reuse the design.
• Difficult to use with todays time constraints.
• Impossible to use as a SoC methodology.- Can
  only use in the Cores used in the SoC.
• How much good does it do anyway ?

11
Closing the Gap between ASIC Custom- Chinnery
Keutzers DAC2000 paper

• Custom Design is six to eight times faster than
  ASIC Design
• The Factors were- 4.00 Architecture Design-
  1.25 Floorplanning- 1.25 Transistor Wire
  sizing- 1.50 Dynamic Logic- 1.90 Process
  Accessibility

12
The Custom Advantage

• About 50 of the advantage is in the skill level
  of the designers.
• About 25 of the advantage is being automated in
  the IC Implementation Tool Set.
• The rest is having access to the process and the
  use of Alternate Libraries.- Minimum use of
  Derivative Libraries can give a major
  performance or area savings boost to even an
  ASIC design.

13
Future Possibilities for Power User Design.

• The increasing use of Alternative Libraries
• Developing synthesizers targeting these
  Alternative Libraries.
• Next generation routing technologies.
• Any other ideas ?

14
The Next Challenge

• It takes 11 - 25 engineers to design a million
  gates.- Methodology and the Tall Thin
  Engineer are the main differentiating factors
  today.
• The goal is 5 - 8 engineers per million gate
  implementation.
• The IC Implementation tool set gets us less than
  half of the way there.
• The Intelligent Test Bench, driving the RTL
  Verification Tool Suite, is the most important
  factor in increasing design productivity.