Page 62 in Chassaing

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Page 62 in Chassaing
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The .start directive links the section name to
start at location address. For the section to
have a valid starting address, the .start
statement for the section must precede the .text,
.data, or .sect directive that defines the
section name.
defines the starting address of the section
.start directive
defines the section
So the program (text) starts at location 809900
and the the data starts at location 809c00.
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DATA
809c00
PBASE
808000
0E970300
809c01
STEPSP
809c02
ATABLE
809c03
162c
809c03
AICSEC
809c04
0001
809c05
4892
809c06
67
4
SINE_VAL 809C08
The .bstart directive aligns the section name to
the next 2n address boundary following the
current section.
0
-1000
0
1000
809C09
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Beginning address of the program 809900
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DIRECT ADDRESSING
The data address is formed by the concantenation
of the eight least significant bits of the data
page pointer (DP) with the 16 least significant
bits of the instruction word. This results in
256 pages of memory with 64K words per page. The
DP must contain the proper value before using
direct addressing.
DP
16 bits of operand
7
AR0 ?
8
AR0 ?
AR0 ?
AR0 28 ?
9
As shown in the previous slide, the timer (TCLK0)
signal is connected to the AICs master clock
(MCLK) signal. The MCLK signal drives all the
key logic signals of the AIC, such as the shift
clock, the switched-capacitor filter clocks, and
the A/D and D/A timing signals. The timer pulses
the TCLK0 signal whenever the timer counter
register (0x0080 8024) counts up to the timer
period register (0x0080 8028) value. Then the
timer counter register resets to zero and repeats.
10
AR0 ?
11
03C1
12
AR0 ?
IOF (IO Flag Register)
13
62H
Place the AIC in reset by bringing XFO pin low.
This is done by writing an 02 to the CPUs IOF
register.
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Contents of ATABLE 809c03
162c
809c03
AR1 ?
809c04
0001
809c05
4892
809c06
67
15
The AIC must stay in a reset condition for at
least 2 TCLK0 cycles.
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17
AR0 ?
18
131
19
131
NOTE for this problem that the input A/D is not
used. Only the D/A is used to generate the sine
wave
20
AR0 ?
21
AR0 ?
22
0E970300
23
0E970300
24
0E970300
The FSX and FSR frame syncs act as active-low
inputs from the AIC. The DX and DR data signals
remain active high. Both transmitted and
received words are 16 bits in length. This
configuration sets the serial port mode for a
standard mode (i.e. not continuous mode) with a
variable data rate. A variable data rate mode
works with AICs timing protocol, whereas a fixed
data rate mode does not.
25
The XMIT (transmit) register is cleared by
writing 0s into each bit.
26
AR0 ?
IOF (IO Flag Register)
A logical 0 resets the AIC a logical 1 brings
the AIC out of reset.
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The RESET line brought low and remains for 100
NOPs.
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Contents of ATABLE 809c03
This instruction establishes AR1 as a pointer to
the table containing the information that sets
the sampling frequency and the bandwidth of the
antialiasing and reconstruction filters, as well
as other constants used by the DSP.
162c
809c03
AR1 ?
809c04
0001
809c05
4892
809c06
67
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Four values are defined in ATABLE. The first and
third values define the sampling rate.
162c
4892
TB
RB
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The second value in table ATABLE sets TA and RA
to zero implying that the sampling frequency will
be determined only by TA and TB.
RA
TA
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The fourth value of the table is the contents of
the control register.
D15
D14
D13
D12
D11
D10
D9
D8
D6
D5
D4
D3
D7
D2
D1
D0
X
X
X
0
1
X
X
X
X
X
1
1
0
0
1
1
Inserts antialiasing filter
The signal varies between ? 3 volts.
Synchronous transmit receive sections
Disables auxiliary input.
Disables loop- back function.
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