Joint Program Seminar

1
Joint Program Seminar

• High-Speed FPGA Design with XC4000

ORNL
September 17, 1999
2
Presentation for ECE-552

• High-Speed FPGA Design with XC4000

ORNL
March 7, 2000
3
Contents

• Xilnix FPGA Overview
• XC4000 Architecture
• Design Flow
• High-Speed Design Examples
• High-Speed VHDL
• High-Speed Simulation
• Hardware Testing
• Design Tips

4
Xilnix FPGA Devices

• High-Density Devices
• XC4000, XC4000XL, XC4000XV
• Virtex
• Low-Cost Devices
• Spartan
• CoolRunner

5
XC 4000 Architecture

• Third generation FPGA
• Sub-micron CMOS process
• Programmable logic blocks and I/O blocks
• Programmable interconnects
• Eight global low-skew clock networks
• Low power
• Six programming modes

6
XC 4000 Architecture
7
XC 4000 Architecture
8
XC 4000 Architecture
9
XC 4000 Architecture
10
XC 4000 Architecture
11
XC 4000 Architecture
12
Design Flow

• Design Entry (Schematic, HDL, Diagram)
• Functional Simulation
• Design Synthesis
• Post-layout Simulation
• Configuration
• Hardware Testing

13
High-Speed Design Examples

• Bus Latches
• Shift Registers
• Counters

14
High-Speed Design Examples Bus Latches
15
High-Speed Design Examples Bus Latches
16
High-Speed Design Examples Bus Latches
17
High-Speed Design Examples Bus Latches
Clock 4 MHz
18
High-Speed Design Examples Bus Latches
Clock 40 MHz
19
High-Speed Design Examples Bus Latches
20
High-Speed Design Examples Bus Latches
21
High-Speed Design Examples Bus Latches
Clock 40 MHz Skew 5 ns
22
High-Speed Design Examples Bus Latches
23
High-Speed Design Examples Bus Latches
24
High-Speed Design Examples Bus Latches
Clock 40 MHz Skew 2 ns
25
High-Speed Design Examples Bus Latches
Clock 100 MHz Skew 2 ns
26
High-Speed Design Examples Parallel-to-serial
Shift Register
27
High-Speed Design Examples Parallel-to-serial
Shift Register
28
High-Speed Design Examples Parallel-to-serial
Shift Register
29
High-Speed Design Examples Parallel-to-serial
Shift Register
Clock 40 MHz
30
High-Speed Design Examples Parallel-to-serial
Shift Register
Clock 100 MHz
31
High-Speed Design Examples Serial-to-parallel
Shift Register
32
High-Speed Design Examples Serial-to-parallel
Shift Register
33
High-Speed Design Examples Serial-to-parallel
Shift Register
Clock 40 MHz
34
High-Speed Design Examples Binary Counter
35
High-Speed Design Examples Binary Counter
36
High-Speed Design Examples Binary Counter
37
High-Speed Design Examples Binary Counter
Clock 20 MHz
38
High-Speed Design Examples Binary Counter
Clock 100 MHz
39
High-Speed Design Examples Binary Counter
40
High-Speed Design Examples Binary Counter
41
High-Speed Design Examples Binary Counter
Clock 100 MHz
42
High-Speed VHDL Design
PRESENT STATE
NEXT STATE
D
Q
COMB
INPUTS
CLOCK
OUTPUTS
COMB
SYNCHRONOUS STATE MACHINE WITH COMBINATORIAL
OUTPUTS
43
High-Speed VHDL Design
SYNCHRONOUS STATE MACHINE WITH COMBINATORIAL
OUTPUTS
44
High-Speed VHDL Design
PRESENT STATE
NEXT STATE
D
Q
COMB
INPUTS
CLOCK
COMB OUTPUTS
SYNC OUTPUTS
D
Q
COMB
CLOCK
SYNCHRONOUS STATE MACHINE WITH SYNCHRONOUS OUTPUTS
45
High-Speed VHDL Design
SYNCHRONOUS STATE MACHINE WITH SYNCHRONOUS OUTPUTS
46
High-Speed Simulation
47
High-Speed Simulation
Clock 70 MHz
Constrained
Unconstrained QA Delay 1.0 ns - 1.6 ns 1.0
ns - 4.3 ns
LA Delay 1.3 ns
48
High-Speed Simulation
49
High-Speed Simulation
50
Design Tips

• Keep the chip usage below 70
• Use global clock networks
• Constrain the net skew
• Use timing constraints in the .ucf file
• Constrain the placement
• Use the floor-plan editor for fine delay
  adjustment

51
Design Tips

• Use VHDL code for state machine design
• Use schematic where timing is critical
• Use Gray code counters
• Use detailed timing data during simulation
• Check the timing of the input signals