CPE 626 The SystemC Language

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CPE 626 The SystemC Language

• Aleksandar Milenkovic
• E-mail milenka_at_ece.uah.edu
• Web http//www.ece.uah.edu/milenka

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Outline

• Writing testbenches
• SystemC types
• Arrays
• Resolved Logic Vector
• Clocks

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Test Benches

• Creating test benches
• one process to generate stimulus, the other one
  to test results
• stimulus are generated in the main program,
  another process test the results
• generated and testing are both done in the main
  program
• Typical approach

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Example Counter
// Filename count.h include "systemc.h" SC_MODU
LE(count) sc_inltboolgt load sc_inltintgt din s
c_inltboolgt clock // input ports sc_outltintgt dout
// output port int count_val // internal
data st. void count_up() SC_CTOR(count)
SC_METHOD(count_up) // Method proc. //
Sensitive to Rising edge clock
sensitive_pos ltlt clock
// Filename count.cpp include "count.h" void
countcount_up() if (load) count_val
din else // Read/Write of local
storage count_val count_val 1 //
Write to Output port dout count_val
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Example Testbench for Counter
// count_stim.cc include "count_stim.h" void
count_stimstimgen() while (true) load
true // load 0 din 0 wait() //
count up, value 1 load false wait()
// count up, value 2 wait() // count up,
value 3 wait() // count up, value 4
wait() // count up, value 5 wait() //
count up, value 6 wait() // count up,
value 7
include "systemc.h" SC_MODULE(count_stim)
sc_outltboolgt load sc_outltintgt din // input
port sc_inltboolgt clock // input port
sc_inltintgt dout void stimgen()
SC_CTOR(count_stim) SC_THREAD(stimgen) sen
sitive_pos (clock)
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Example Main
include "count.h" include "count_stim.h" includ
e "display.h" int sc_main(int argc, char
argv) sc_signalltboolgt LOAD
sc_signalltintgt DIN, DOUT // clock sc_clock
CLOCK("clock", 20) int sim_time 0 if
(argc2) sim_time atoi(argv1) if
(sim_time0) sim_time 1000
count u_count ("count") u_count.load(LOAD)
u_count.din(DIN) u_count.dout(DOUT)
u_count.clock(CLOCK) count_stim
u_count_stim("count_stim") u_count_stim.load(LO
AD) u_count_stim.din(DIN)
u_count_stim.dout(DOUT) u_count_stim.clock(CLOC
K) display u_display("display")
u_display.dout(DOUT) sc_initialize()
sc_start(sim_time) return(0)
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SystemC Types

• SystemC programs may use any C type along with
  any of the built-in ones for modeling systems
• long, int, char, short, float, double
• SystemC Built-in Types
• sc_bit (0, 1), sc_logic (0, 1, X, Z)
• Two- and four-valued single bit

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SystemC Types

• SystemC Built-in Types
• sc_intltngt, sc_unintltngt
• 1 to 64-bit signed and unsigned integers
• sc_bigintltngt, sc_biguintltngt
• arbitrary (fixed) width signed and unsigned
  integers
• sc_bv, sc_lv
• arbitrary width two- and four-valued vectors
• sc_fixed, sc_ufixed
• signed and unsigned fixed point numbers
• User defined constructs

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Ports, ReadingWriting ports
sc_inltporttypegt // input port of type
porttype sc_outltporttypegt // output port of type
porttype sc_inoutltporttypegt // inout port of type
porttype
porttype may be any of the types discussed

• ReadWriting ports
• Use read() or write() methods, or
• Use assignment operator

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Arrays
sc_inltsc_logicgt a32 // creates ports a0 to
a31 // of type sc_logic sc_signalltsc_logicgt
i16 // creates signals i0 to // i15 of
type sc_logic
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Resolved Logic Vector

• More than one driver is driving a signal

Resolved logic vector port
sc_in_rvltngt x //input resolved logic vector n
bits wide sc_out_rvltngt y// output resolved logic
vector n bits wide sc_inout_rvltngt z // inout
resolved logic vector n bits wide
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Resolved Vector Signals

• Used to connect resolved logic vector ports

Resolved logic vector signal
sc_signal_rvltngt sig3 // resolved logic vector
signal // n bits wide
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Clocks

• Create clock object named clock1
• clock period is 20 time units
• duty cycle is 50
• first edge will occur at 2 time units
• first value will be true

sc_clock clock1("clock1", 20, 0.5, 2, true)