Multilevel Interconnect Architectures

1
Multilevel Interconnect Architectures for
Gigascale Integration (GSI)
A thesis proposal Raguraman Venkatesan Advisor
Prof. James D Meindl Co-advisor Prof. Jeffrey A
Davis
Georgia Institute of Technology, Atlanta April
29th, 2002 Sponsored by SRC and DARPA
2
Outline

• Problem Statement
• Origin and History of the Problem
• Proposed Research and Current Status
• Work remaining to be done
• List of Contributions
• List of Publications

3
Outline

• Problem Statement
• Origin and History of the Problem
• Proposed Research and Current Status
• Work remaining to be done
• List of Contributions
• List of Publications

4
Problem Statement

• Interconnects are the bottleneck, not transistors
• Key technology metrics
• Speed
• Power
• Cost

Source Meindl et al., IEDM, 2001
5
Power Density Gets Worse
Source Shekhar Borkar, Intel Corporation
6
Interconnect Power Dissipation

• Interconnect power
• 30-60 of total power dissipation !
• Power-aware interconnect design methodology
  strongly needed

Source Chandra, Kapur and Saraswat, IITC, 2002
(in press)
7
Multilevel Interconnect Layers

• Lower cost gt Optimal design of metal layers

Source International Technology Roadmap for
Semiconductors (ITRS), 1998
8
Bottomline

• Design multilevel interconnect system properly !!

9
Outline

• Problem Statement
• Origin and History of the Problem
• Proposed Research and Current Status
• Work remaining to be done
• List of Contributions
• List of Publications

10
Origin and History of the Problem

• Rents rule
• T Number of I/Os
• N Number of logic gates
• p Rents exponent
  p0.6, k4, N1E9
• k Rents coefficient T 1E7

Source Landman Russo, IEEE Trans. Computers,
Dec 1971
11

• Stochastic Interconnect Wiring Distribution
• a priori prediction of wire length and number of
  wires

Source Davis, De and Meindl, Trans. Electron
Devices, Mar 1998
12

• Wire Sizing
• Reverse scaling
• 2 wire widths Local global
• 3 wire widths Local, semi-global and global
• Double pitches for every 2 metal layers
• 30 scaling rule
• Linear dimensions
  30
• Area
  50

Source Sai-Halasz Proc. IEEE, Jan 1995
13

• Wire layer assignment
• Input Wire pitches
• Delay dependent layer assignment
• Optimum number of repeaters
• Cost function Number of metal layers
• Computationally inefficient algorithm
• Requires several iterations
• Area-inefficient solution

Source Kahng and Stroobandt, SLIP Workshop, 2000
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Origin and History of the Problem

• Developed 3-tier interconnect design methodology
• Local
• Semi-global
• Global
• Using
• Wire length information (Stochastic Distribution)
• Pitch information (rc time delay models)

Source Davis, De and Meindl, Trans. Electron
Devices, Mar 1998
15
Outline

• Problem Statement
• Origin and History of the Problem
• Proposed Research and Current Status
• Work remaining to be done
• List of Contributions
• List of Publications

16
Proposed Research Tasks

• Task I Optimum n-tier methodology
• Task II Repeater insertion in n-tier
  methodology
• Task III Complete physical models for
  transient
• response of distributed rlc
  lines
• Task IV Compact physical models for time
  delay,
• crosstalk and repeater
  insertion
• Task V Impact of inductance on multilevel
• interconnect architectures
• Task VI Impact of parameter variations on
  clock skew
• Task VII Develop MINDS (Multilevel
  Interconnect Network
• Design Simulator)

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Task I Optimal n-tier multilevel
interconnect methodology

• New n-tier methodology
• ASIC case study from ITRS 100nm generation
• Three optimizations
• Macrocell Area
• Clock Frequency
• Number of metal levels

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Some definitions
Level single layer of parallel interconnects

Pair Two adjacent orthogonal levels having same
dimensions
Tier Collection of Pairs having same dimensions
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Optimal Multilevel Architecture

• Area is wire limited

Available area Area required
for wiring
20

• rc models for interconnect time delay
• clock frequency, wire length wire
  pitch

Source Sakurai, Trans. Electron Devices, 1993
21
n Tier Interconnect Network
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ITRS 100nm Case Study

• 100 nm technology
• ASIC macrocell with 11.3M logic gates
• ( 68M transistors)
• Copper interconnects
• n8 metal levels

Source International Technology Roadmap for
Semiconductors (ITRS), 1998
23
Conventional design
Double pitches for every pair of layers
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Optimum n-tier architecture
A Min. area B Max. freq C Min. levels
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Optimization results

• compared to doubling of pitches design

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Task II Repeater insertion in
n-tier methodology

• Repeater insertion models and methodology
• ASIC case study from ITRS 100nm generation
• Four optimizations
• Macrocell Area
• Power dissipation
• Clock Frequency
• Number of metal levels

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Advantages of Repeaters

• Single driver (No repeaters)

• With repeaters

Source Bakoglu and Meindl, Trans. Electron
Devices, May 1985
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Sub-optimal repeater design
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Top-down Repeater Insertion Methodology
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Minimizing Macrocell Area
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Minimizing Macrocell Area
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Minimizing Power Dissipation
Area and power are minimized simultaneously!
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Maximizing Clock Frequency
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Minimizing Number of Levels
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Optimization Results

• compared to n-tier design without
  repeaters

36
SWOT Analysis

• Strengths Novel layer width estimator
• Weaknesses System level tool makes
  approximations
• Opportunities Enables technology forecasting
  for any future generation
• Threats Unless the future generation uses
  wireless interconnects !

37
Task III Complete Transient Model for
Distributed rlc Lines with Cload

• Previous Work
• Model derivation
• Single and two coupled line transients

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Previous Work

• Rochesters model- Time delay and repeater
  insertion in rlc lines. Expressions are curve
  fitted, not analytical.

Source Ismail and Friedman, Trans. VLSI, Apr
2000
39
Previous Work

• Georgia Tech - Compact models for distributed rlc
  lines
• Use modified Bessel functions
• Time domain response of finite, open-ckt
  distributed rlc line
• Compact expressions for time delay and crosstalk

Source Davis and Meindl, Trans. Elec. Dev,
Nov 2000
40
Problem Definition

• Transmission line theory Multiple reflections
  at
• load
  and source ends

41
Basis Variables
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Single Line Transients
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2 Coupled Line Transients
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Task IV Compact Models for
Time Delay, Crosstalk
Repeater Insertion

• Unified time delay model
• Unified crosstalk model
• Optimum repeater insertion models
• New design plane

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Unified Time Delay Model

• Unified Applicable to rc and rlc lines

46
Unified Time Delay Model
Source Ismail and Friedman, T. VLSI, Apr 2000
47
Unified Crosstalk Model
Source Cao et al. IEDM 2000
48
Repeater Models
49
Repeater Models
50
Repeater Models
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Can Repeaters Reduce Crosstalk?

• Inserting repeaters
• Thinner wires, same delay
• More RC gt less LC behaviour
• Repeaters increase
• more grounding
• Inserting repeaters
• might decrease crosstalk
• without increasing time delay!

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Design Plane
53
Design Plane
54
Design Plane
55
Outline

• Problem Statement
• Origin and History of the Problem
• Proposed Research and Current Status
• Work remaining to be done
• List of Contributions
• List of Publications

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Task V Effects of Inductance on n-tier Design

• Investigate effects of inductance on repeater
  insertion in multilevel interconnect
  architectures
• Optimum aspect ratio for different tiers
• Impact of non-ideal ground return paths on
  repeater-inserted multilevel interconnect systems

Source Naeemi et al., IEDM 2001
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Task VI Effects of Parameter Variations
on Clock Skew

• Previous work Used rc models
• Model a high speed clock distribution network
• Use new compact rlc models to investigate clock
  skew

Source Kowalczyk et al., ISSCC 2001
Anderson et al., ISSCC 2002
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Task VII MINDS

• Multilevel Interconnect Network Design Simulator
• Current capabilities
• n-tier design, with repeaters, using rc models
• Via blockage, power/ground blockage
• Variable pitches, variable wiring efficiency
• Enhancements
• Include rlc models
• Optimum aspect ratio
• Non-ideal return paths

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Timeline of Work Left
60
Outline

• Problem Statement
• Origin and History of the Problem
• Proposed Research and Current Status
• Work remaining to be done
• List of Contributions
• List of Publications

61
List of Contributions
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List of Publications

• Conference papers
• R.Venkatesan, J.A.Davis and J.D.Meindl,
  Performance enhancement through optimal n-tier
  multilevel interconnect architectures,
  Proceedings of the Twelfth International IEEE
  ASIC/SOC conference, Washington DC, Sept. 15-18
  1999, pp. 19-23.
• J.A.Davis, R.Venkatesan, K.A.Bowman and
  J.D.Meindl, Gigascale integration (GSI)
  interconnect limits and n-tier multilevel
  interconnect architectural solutions, Proceedings
  of the International Workshop on System Level
  Interconnect Prediction (SLIP), San Diego, April
  8-9 2000, pp. 147-148.
• R.Venkatesan, J.A.Davis, K.A.Bowman and
  J.D.Meindl, Optimal repeater insertion for n-tier
  multilevel interconnect architectures,
  Proceedings of the Third International
  Interconnect Technology Conference, San
  Francisco, June 5-7 2000, pp. 132-134.
• R.Venkatesan, J.A.Davis, K.A.Bowman and
  J.D.Meindl, Minimum power and area n-tier
  multilevel interconnect architectures using
  optimal repeater insertion, Proceedings of the
  International Symposium on Low Power Electronics
  and Design, Rapallo/Portofino Coast, Italy, July
  26-27 2000, pp. 167-172.
• J.D.Meindl, R.Venkatesan, J.A.Davis, J.W.Joyner,
  A.Naeemi, P.Zarkesh-Ha, M.Bakir, T.Mule, P.A.Kohl
  and K.P.Martin, Interconnecting device
  opportunities for gigascale integration (GSI),
  International Electron Devices Meeting (IEDM),
  Washington D.C., Dec 2001, pp. 525-528.
• R.Venkatesan, J.A.Davis and J.D.Meindl, A
  complete physical model for distributed RLC
  interconnects - transient voltage, time delay and
  crosstalk, to be published in the proceedings of
  the Design Automation Conference, New Orleans,
  June 2002.
• A.Naeemi, R.Venkatesan and J.D. Meindl,
  System-on-a-chip global interconnect
  optimization, submitted to the ASIC/SOC
  Conference, Rochester, Sept 2002.
• R.Venkatesan, J.A.Davis and J.D.Meindl, Time
  delay, crosstalk and repeater insertion models
  for high performance SOCs, submitted to the
  ASIC/SOC Conference, Rochester, Sept 2002.

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List of Publications

• Journal papers
• J.A.Davis, R.Venkatesan, A.Kaloyeros, M.Bylansky,
  S.J.Souri, K.Banerjee, K.C.Saraswat, A.Rahman,
  R.Reif and J.D.Meindl, Interconnect limits on
  Gigascale integration (GSI) in the 21st century,
  Proceedings of the IEEE - special issue on limits
  to semiconductor technology, Vol. 89, No. 3,
  March 2001, pp. 305-324.
• R.Venkatesan, J.A.Davis, K.A.Bowman and
  J.D.Meindl, Optimal n-tier multilevel
  interconnect architectures for gigascale
  integration, IEEE Transactions on VLSI Systems -
  special issue on System Level Interconnect
  Prediction, Vol. 9, No. 6, Dec 2001, pp. 899-912.
  
• J.W.Joyner, R.Venkatesan, P.Zarkesh-Ha, J.A.Davis
  and J.D.Meindl, Impact of three dimensional
  architectures on homogenous digital circuits ,
  IEEE Transactions on VLSI Systems - special issue
  on System Level Interconnect Prediction, Vol. 9,
  No. 6, Dec 2001, pp. 922-928.
• R.Venkatesan, J.A.Davis and J.D.Meindl, A
  complete physical model for distributed rlc
  interconnects with capacitive load Part 1
  Single line transients and coupled line
  crosstalk, to be submitted to the Trans. Electron
  Devices.
• R.Venkatesan, J.A.Davis and J.D.Meindl, A
  complete physical model for distributed rlc
  interconnects with capacitive load Part 2
  Unified models for time delay, crosstalk and
  repeater insertion, to be submitted to the Trans.
  Electron Devices.
• Book chapter
• J.A.Davis and J.D.Meindl, Interconnect design
  issues and opportunities for Gigascale
  Integration, Kluwer Academic Publishers, in
  press.

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Acknowledgements

• Prof. James Meindl
• Prof. Jeff Davis
• Prof. Scott Wills
• Jennifer Tatham
• Dr. Keith Bowman
• Dr. Payman Zarkesh-Ha
• Dr. Azeez Bhavnagarwala
• Dr. Chirag Patel

• Azad Naeemi
• James Joyner
• Qiang Chen
• Tony Mule
• Raghunath Murali
• Hiren Thacker

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Thank You!