HardwareSoftware CoDesign

1
Hardware/Software Co-Design

• Bassam Tabbara
• GSRC System Level Design Group
• Alberto Sangiovanni-Vincentelli
• University of California at Berkeley

2
Domain of Application

• Mixed hardware/software systems
• System on Chip (SoC)
• Embedded Systems
• airplanes, cars ...
• telecommunications
• kitchen appliances

3
Goals

• Design/Implementation Verification
• (Formal Verification, simulation, rapid
  prototyping)
• Hardware, Software, and Interface Synthesis
• different hardware and software implementation
  styles
• Designer can concentrate on high level issues

4
Methodology

• Separation between function, and communication
• Unified refinable formal specification model
• facilitates system specification
• implementation independent
• eases HW/SW trade-off evaluation and partitioning
  

5
Co-Design Methodology
6
POLIS Co-design Environment

• Specification FSM-based languages (Esterel, ...)
• Internal representation CFSM network
• Validation
• High-level co-simulation
• FSM-based formal verification
• Rapid prototyping
• Partitioning based on co-simulation estimates
• Scheduling
• Synthesis
• CDFG based code synthesis for software
• Logic synthesis for hardware

7
Model Network of CFSMs
8
POLIS Co-design Environment
9
Overview Summary

• Hardware/Software co-design requires a new
  methodology that is independent of the
  implementation
• Separation between function, and communication
• Unified network of CFSMs model for hardware and
  software
• Automatic synthesis of
• Hardware
• Software
• Interfaces
• RTOS

10
Berkeley Team Members

• Luca Carloni GSRC
• Specification
• Fernando De Bernardinis
• Applications
• Harry Hsieh GSRC
• Formal Verification
• Synchronous Equivalence
• Jonathan Martin
• Specification
• Software Synthesis
• Roberto Passerone GSRC
• Specification
• Interface Synthesis

• Claudio Pinello
• Applications
• Felix
• Marco Sgroi GSRC, BWRC
• Specification
• Synthesis
• Scheduling
• Bassam Tabbara GSRC, NexSIS
• Optimization
• Synthesis
• Co-simulation
• Alberto Sangiovanni-Vincentelli
• Professor

11
Useful Links

• The POLIS system is freely available on the WEB
• http//www-cad.eecs.berkeley.edu/polis
• Uses the Esterel as front-end
• http//www.inria.fr/meije/esterel
• Uses VHDL or the Ptolemy system for co-simulation
• http//ptolemy.eecs.berkeley.edu
• Feedback to
• polis-questions_at_ic.eecs.berkeley.edu