Implementing TCP using HDL

1
Implementing TCP using HDL

• By
• Ajay Bhargava
• Boudhayan Basu Choudhuri
• Jason Wertz

2
Outline

• Objectives
• State Machine Flow Charts
• Block Diagram/Interfaces
• Design and Test Plan
• Current Status
• Issues

3
Objectives
This design is aimed to achieve following
objectives

• Implementing server side TCP functionality

• Supporting only one TCP connection at a time

4
Logic for Main_SM
E
LISTEN
Wait for rcv_data_valid
? rcv_data_valid
Read Data from IP buffer
Is SYN Received ?
NO
Discard the data
YES
Make SYN-ACK Packet
C
Wait for Send_ready from IP layer
? Send_Ready
Write data into IP buffer
Set Send_data_valid for IP
! Send_data_valid
A
5
A
Wait for ACK till Timeout occurs
Is ACK Received ?
NO
C
YES
Relinquish control to TX_SM
! TX_SM_INIT, !RX_SM_INIT
Connection established with the client. Wait
indefinite till Main_SM_Resume is set by TX_SM.
? Main_SM_Resume
D
Start making Finish packet.
Wait for Send_ready from IP layer
? Send_Ready
Write Finish packet into IP buffer
! Finish_Svr
Set Send_data_valid for IP
B
6
B
Time-Out
Wait for ACK of FINISH from client till Timeout.
D
? Ack_Finish_Svr
Time-Out
Wait for FINISH from Client till Timeout.
? Finish_Client
Start making Ack_Finish_client for the
Finish_Client and send it to IP layer.
Wait for Send_ready from IP layer
? Send_Ready
Write Ack_Finish_client packet into IP buffer
! Ack_Finish_Client
Wait for 2 MSL Timeout
Reset all the connection variables
E
7
Logic for TX_SM
D
TX_SM_Idle, wait till INIT message
? TX_SM_INIT
B
TX_SM_Start
! Send_ready
? No_Data
Create TCP Header
Relinquish Control to Main_SM
C
Wait for send_data_valid from the Http
! Main_SM_Resume
? Send_data_valid
Read the data from the http buffer
Reset variables being used locally
Create TCP packet from the data read
D
Wait for Send_ready from the IP layer
? Send_ready
Write Send_data into the buffer
Relinquish Control to RX_SM
A
8
A
Wait for ACK Timeout Period.
Wait for ACK Timeout Period.
! ACK_RX_SM
Is ACK Received ?
NO
C
! Repeat_request
! Send_ready
YES
B
9
Logic for RX_SM
B
RX_SM_Idle, wait till INIT message
? RX_SM_INIT
RX_SM_Start
C
Wait for rcv_data_valid
? rcv_data_valid
Read the data from the buffer
Is data packet ACK ?
NO
Discard the packet
!ACK_RX_SM
YES
Relinquish control to TX_SM
Wait to regain control from the TX_SM
A
10
A
Check No_Data ?
NO
C
YES
Reset variables being used locally
B
11
Interface Diagram
send_ready
start_pos
rcv_data
rcv_data_valid
send_data
send_data_valid
State Machine for Connection Management
32
3
?
8
8
Transmission Control Block
32
3
3
32
State Machine for Sending Data
State Machine for Receiving ACKs
Tx_Busy
Rx_Busy
32
8
src_IP _addr
rcv_data
rcv_data _valid
send_ready
send_data _valid
send_data
dest_IP _addr
12
TestingEach Piece
13
TestingInternal Tests
 
Testbench
Main
TCB
XMTR
RCVR
14
TestingTCP Module
Server
Client
RAM
RAM
TCP
TCP
RAM
Further Testing can be done by substituting HTTP
modules for the top two pieces of RAM.
15
Current Status

• External interface mostly identified
• Internal interface finalized
• State machine divided up into three Sections
• Code is in progress
• Working on resolving some timing issues

16
Issues

• Can we get a precalculated checksum from HTTP for
  the data?
• Are buffers possible?
• If buffers arent possible, there are going to be
  many timing issues to be worked out?
• After a ready flag goes high, how many clock
  cycles till data is on the line? How many clock
  cycles will it remain there?
• What if one layer cant provide constant data at
  the rate of the byte clock? How will gaps in
  data be treated? Can you pause in the middle of
  sending data? How will that affect other layers?
• Others timing issues?

17
Any Questions?