Versatile Calculator

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Versatile Calculator

• By
• Dilip Patlolla
• Roopa Channappa
• Electrical and Computer Engineering
• University of Tennessee
• Knoxville

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Versatile Calculator

• This Project deals with the design of a block,
  which is part of the MIPS (Micro Computer without
  Interlocked Pipeline Stages) Processor
  architecture. In this project, a Data Path and
  Control Unit are implemented to carry the design.
  The block is designed to work as a calculator
  where the user provides the instruction and the
  data on which the operation is to be performed.

3
Design Flow

System Requirements
Architectural Specifications
Behavioral Description
Structural Description
Synthesis
Libraries
Simulation
Placement and Routing
Physical Implementation
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Specifications

• Instruction Memory
• Splitter
• Register
• ALU
• Display Controller
• BIST
• Clock

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Block Diagram
BIST
Control Unit
opcode
input
go
digit
do
Instruction splitter
Register
ALU
Display Controller
data1
opcode
carry
RESET
Data 2
borrow
MUX
seg
Data 1
result
BIST
CLOCK
clock
Result to memory
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System Requirements

Address(30) Slide switches(k13,k14,j13,J14)
4
8
FPGA
BIST(L13)
1
Seven Segment Display
8
1
DO(M13)
1
Go(M14)
8
Clock (T9)
Reset(L14)
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Instruction Set Memory

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Instruction set
15
0
9
4
10
Opcode
DATA 1
DATA 2

• The instruction set is of 16 bit width
• With three parts
• DATA 1 of 6 bit length
• DATA 2 of 6 bit length
• Opcode of 4 bit length

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Opcodes

• Operations
• 0001 add - data 1 data 2
• 0010 subtract - data 1 data 2
• 0011 increment - data1 1
• 0100 decrement - data1 - 1
• 1001 add - result data1
• 1010 subtract - result - data 1
• 1011 increment - result 1
• 1100 decrement - result - 1

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Instruction Splitter

• This block splits the instruction set into
  the three parts of data1, data2 and op code

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Register
12
Multiplexer

• Sends the output based on the select input
  received from Control Unit

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Arithmetic Logic Unit
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ALU

• Computes the result.
• Indicates the Carry or Borrow based on the
  operation result
• Output is zero when reset

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Control Unit

• Sends operation codes to ALU
• Sends the required control codes to the
  Multiplexer and Memory based on the input opcode

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Display Controller

• Accepts a 6-bit binary number between 0 and 63
  (output of the ALU)
• Converts binary number to a 2-digit BCD
  representation
• Generates appropriate logic levels to drive
  7-segment display

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Final Single Block Diagram
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Xilinx Block Diagram
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Difficulties

• Timing issues
• Implementing few Instructions

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MIPS Processor
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Summary and Conclusion

• This is an approximate basic sub part of a MIPS
  processor which is shown to work as a calculator
  which can be further developed into a ready to
  use core in MIPS architecture.

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Scope for Development

• These cores can be mixed with add-in units such
  as SIMD systems, various input/output devices,
  etc.
• MIPS cores have been commercially successful, now
  being used in many consumer and industrial
  applications. MIPS cores can be found in newer
  Cisco and Linksys routers, cable modems and ADSL
  modems, smartcards, laser printer engines,
  set-top boxes, robots, handheld computers, Sony
  PlayStation 2 and Sony PlayStation Portable.

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• THANK YOU