Implementing SumsofProducts

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Implementing Sums-of-Products
We find And-Or structures like this all of the
time.
2 x 2-input And-Or-Invert
3 x 2-input And-Or-Invert
Although wiring is simpler, part selection is now
harder
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Programmed Array Logic (PAL)
Fusable links Links may be blown. Once blown,
they are permanently open.
Fusable links
Current
Complex wiring is replaced with programming
PALs support multiple functions of the same inputs
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PAL Example
B
C
A
Program F1ABAC
Blow all unused links
F1
Program F2ABC
Leave unused product terms alone (AABBCC)
ABC
F2
0
C
C
B
B
A
A
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Schematic Representation of PALs
xs mark Connections Fuses are not blown
DC
DC
F1DC DC BA BA
BA
BA
F2DA CB DCBA
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The Way Things Are Real PALs
Tristate Buffer
Input pin
I/O pin
Input pin
Output Inversion Ctrl
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A More General Idea
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Sharing Product Terms in a PLA
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Programming Devices

• PLAs and PALs are programmed using a special
  programmer

• Most devices are erasable
• Dont use fuses, but instead electrical methods
  of programming
• Erased by exposing to UV light

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Macrocells
Altera Macrocell
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CPLDs

• Complex Programmable Logic Devices
• Contain from 10-1000 macrocells
• Each macrocell is equivalent to around 20 gates
• Support up to 200 I/O pins

• The key resource in a CPLD is interconnect
• Tradeoff between space for macrocells and space
  for interconnect
• Careful design will limit the connections between
  macrocells

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Electrically Erasable PLDs

• Conventional PLDs are either
• One-time programmable
• UV Erasable
• Must be placed in a programmer to program them

• EE PLDs can be programmed and erased in place
• A small (four wire) connection to a computer is
  needed
• Once programmed, will retain program indefinitely
• Never have to take the chip out of its circuit

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Field Programmable Gate Arrays
FPGAs are based on Look-up Tables (LUTs)
A LUT is simply a representation of a truth table
Example Three-input LUT
The function is programmable any LUT can be
programmed to be any function
3-input Look-up Table
FPGAs are just a whole lot of LUTs with lots of
interconnect
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FPGA Organization
00110111
11011010
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FPGAs

• FPGAs are based on SRAM
• Lose programming when power is turned off
• Can be programmed by a computer or by a special
  EPROM

• Capacity
• May have up to 10,000,000 gate equivalent
• Up to 1,200 I/O pins