Active Packaging: Power Management for Nanoprocessors

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Active Packaging Power Management for
Nanoprocessors

• Raj Nair, ComLSI Inc.
• Presented to the First AZ Nanotechnology
  Symposium
• March 16, 2006

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Prologue

• With a billion connected pcs, cutting
  nanoprocessor power by ½ reduces energy
  consumption by 50 Giga watts!
• Advanced power management is innovation leading
  to energy efficiency

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Scaling of Dimensions
1
1
1
0.49
0.7
Smaller, faster cheaperOr so it was!
0.7
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Power Related Prediction in 2001
References Raj Nair 2001 Intel Assembly
Technology Journal Invited Paper on
Pathfinding 2002 Intel Technology Journal paper
Emerging Directions for Packaging
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Consequences
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Leakage in Nanometer CMOS
Leakage power now equals active power! And both
are exponential with Vdd
Source S. Narendra A. Chandrakasan Leakage in
Nanometer Technologies, Springer Publications,
2005
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Supply Voltage Is Key

• Lower supply voltage much lower power
• Active power is quadratically related ( ? V2)
• Leakage power is exponential (? eV )
• For a Nanoprocessor (or SoC), this is multiple
  supplies on chip independent dynamic control
• And fine, high-bandwidth control of noise

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Active Noise Regulators

• Active Noise Regulators (ANRs) sense/regulate
  noise in a nanoprocessorss voltage islands
• ANRs enhance (not replace) nanoprocessor power
  delivery infrastructure

Reference Raj Nair Donald Bennett Power
Management Designline article http//www.powermana
gementdesignline.com/howto/175800373
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Active Noise Regulation
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Prediction Validation

• 2001 iATTJ 1 The Silicon Sandwich integrates
  all the components for power conversion into a
  multicomponent active interposer that is bonded
  to the CPU and sandwiched between two heat
  sinks. The name derives from the structure and
  the many technologies integrated.
• 2006 EETimes 3 A second ISSCC paper discusses
  a prototype method for supporting multiple power
  supply rails on chip by using a new all-CMOS,
  fast voltage regulator. The technique would be
  especially useful for running different cores at
  different supply voltages on multicore CPUs,
  Rattner said. "This is a very important
  technology for which we have high hopes," he
  added. Bringing the new thin films into high
  volume fabs and getting the inductors on chip are
  major challenges toward commercializing the
  technology over the next three to four years, he
  added.

References 1, 2 Raj Nair, 3 EETimes
article 2001 Intel Assembly Technology Journal
Invited Paper on Pathfinding / US pat.
pub.20030081389 February 06, 2006 EETimes Intel
CTO calls for better chip-design tools to beat
process variance
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ComLSI

• Products / Service offering
• PowerESL Tools and expertise for IC power
  integrity
• Analog / Mixed-Signal IP in development for DVI /
  HDMI / Power Management applications
• Analog / Custom design services
• Patents 5 pending in ANR / AVP technology
• 40 authored, 34 issued
• Team 50 years of technology mgmnt. mktg.

Contact Raj Nair, President, raj_at_anasim.com
www.comlsi.com 1 [phone]