A New Delay Model for Simultaneous Tononcontrolling Transitions

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A New Delay Model for Simultaneous
To-non-controlling Transitions
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Outline

• Introduction
• Modeling approach
• Captured delay phenomena an example
• Delay phenomena
• Delay model
• Library Characterization
• Summary
• Process Flow

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Introduction Previous and New Delay Models

• Our previous delay model
• Identify important delay phenomena
• Capture all delay phenomena in a two-input gate
• Improved new model
• Handle
• Simple gates with more than two inputs
• More simultaneous switching
• Charge sharing
• Early transitions
• Applicable to timing analysis

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Introduction Empirical Model

• Advantage
• Delay effects of phenomena need not to be
  considered separately and then combined together.
  Given input waveforms, the simulator takes care
  of all relevant effects.
• Critical issue
• Identify the cases where targeted delay phenomena
  are excited, to ensure their effects are
  captured.
• Simulation scenario Characterized by such
  factors as the vectors, transition times, skews,
  and the initial states of internal capacitances.

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Modeling Approach Comparisons

• Other people's models
• Based on few major observations
• Without validation over proper input
  combinations, each of them has significant errors
  in some operation conditions
• Our approach
• starts with intensive simulations by varying all
  input variables (input slews, input skews, and
  states of internal capacitances)
• identify major delay phenomena
• measure magnitudes of each phenomenon
• find input waveforms exciting these phenomena
• develop an empirical model with automatic
  characterization

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Captured Delay PhenomenaSkew-Delay Relation

• Input transition time TX TY

Vc0Vdd
Vc00
Y late
X late
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Delay PhenomenaFor Simultaneous
To-non-controlling Transitions

• Short circuit current
• Initial states of internal capacitances
• Stopping early discharge
• Impedance match
• Miller effect
• Body effect

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Delay PhenomenaShort Circuit Current

• Gate output starts to switch when the current
  that charges output is smaller than the current
  that pulls it down

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Delay Phenomena Initial States of Internal
Capacitances

• Activating a rising transition at both X and Y
• C Status of C after application of V1 but
  before
• application of V2

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Delay PhenomenaStopping Early Discharge

• Two skew-delay curves may have the same
  pin-to-pin delay but different simultaneous delay

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Delay PhenomenaImpedance Match

• Charge at the internal capacitance may reduce
  gate delay due to a better match between the
  pull-down transistors

For transition on X IY? VYVC- VC2/2
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Delay PhenomenaMiller Effect

• charges are transferred from gate inputs to gate
  outputs and slow-down output transitions

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Delay PhenomenaBody Effect

• threshold voltage of transistor n1 increases due
  to Vsb gt 0

If Vsn1 gt 0, Vsb of transistor n1 gt 0 ? Vthn1
increase
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Delay PhenomenaMagnitudes

• Gate delay with/without noted phenomena
• Based on minimum-size 2-input NAND gate with a
  minimum load

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Delay PhenomenaCapture by Input Waveforms

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Delay Model - Basic Principles of Classification

• Divide the delay model into several cases where
  each case has its own formulae for transition
  time and delay.
• Use many coefficients to improves accuracy.
• In our classification, each discrete variable
  (library cell, input position, and number of
  pre-charged internal capacitances) is enumerated.
  
• For each combination in the enumeration, we
  develop a set of formulae whose input variables
  are the continuous variables in the original
  delay functions (input transition times and
  skew).

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Delay Model - BasicModeling Each Classification

• Vary TX and TY, simulate skew-delay relation
• For each pair of TX and TY, delay is approximated
  by 3/4 point piecewise linear function(4
  pre-discharged)
• Curve-fitting to find formulae for each
  coordinator of these points as functions of TX
  and TY

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Delay Model Extensions

• Simple gates with more than two inputs enumerate
  more cases
• More simultaneous switching find tight proper
  upper/lower bounds instead of a single value
• Charge sharing bounded by characterized cases
• Early transitions bound its maximal delay
  effect
• Load add degree 2 polynomials to approximate
  load effects
• Applied to timing analysis develop formulae for
  timing analysis based on this model

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Delay Model Run Time Comparison

• Three-simultaneous delay takes about four times
  of operations, compared to two-simultaneous
  delay.
• Computation for simultaneous delay is invoked
  only if simultaneous waveforms are identified in
  gate inputs.

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Delay Model Experimental Results
All internal capacitances pre-discharged
All internal capacitances pre-charged
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Cell Library CharacterizationConsider Different
Gate Types

• We have demonstrated the approach on simple gates
• Internal capacitances' states can still be
  enumerated case by case for every cell
• Main challenge is modeling simultaneous input
  transitions
• If at most two such transitions exist in a cell,
  our characterization applies directly
• valid for XOR, tri-state buffer, flip-flops,
  multiplexors, ...
• Dynamic gates can use the same approach as static
  gates
• We will extend our model for complex gates in the
  future

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Library Characterization Automation Motivation

• Our approach uses a delay model for primitive
  gates that needs timing information not currently
  available in common cell libraries.
• Pin-to-pin delay model
• Delay(input transition time, output load)
• Our delay model
• Delay(input transition time, output load,
• input skews, states of internal
  capacitances)
• Automated development of our delay model will
  facilitate the use of our tool to real circuits.
• More advantages
• Reduce characterization effort for process
  changes
• Enable modeling for multiple process corners

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Library Characterization Automation Flow Chart
for Primitive Gates
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Summary

• We have developed a general delay model for
  capturing simultaneous switching on
  to-non-controlling transitions.
• This model is more accurate than all previous
  gate-level delay models.
• We automated the development of the delay model.
• This model is applicable to timing analysis.
• This model can handle partially specified input
  logic values to capture tighter timing ranges -
  helps prune search space in timing-based ATPG

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Process Flow