Design%20Review

1
Design Review
2
Specifications

• Minimum
• 64 port OC-48, aggregate capacity of 160Gbps,
  Fair Queuing.
• Extra
• RED
• MPLS, QoS
• Multicast
• Scalability

3
Components

• Input Port processing (IPP)
• Buffers
• Switch Scheduling
• Output port processing
• Fair Queuing

4
Input Port Processing

• Line termination and data link processing
• Break variable length packet into fixed length
• Lookup routing information
• Process packets at "line speed i.e. close to 5
  million routing lookup per second.
• Do simple IP packet processing functions
• Decrease TTL, Checksum etc.
• MPLS or Hardware Filters

5
Possible Solutions for IPP

• Transceiver for line termination and PHY
  processing
• HFCT-5402D by Agilent (HP)
• VSC8140 by Vitesse
• Framer for fixed size cells
• VSC9112 by Vitesse
• Network Processor
• IXP1200 by Intel (Level One)
• APP1200 and APP1400 by Agere
• Generic micro-processor

6
Where to Queue?

• Input port
• Does not require high fabric speedup.
• OPP can be done at reasonable speeds
• Difficult to do output scheduling (FQ)
• Output port
• Easy to schedule packets on the link (FQ)
• Fabric and OPP have to have high speedup.

7
Buffers

• Our initial decision
• Buffer packets on the input port
• Handle FQ at the input port (somehow)
• Use standard SDRAM for buffers
• PC-100 10ns access latency
• Dimension buffer by simulation
• Buffers for each input port.

8
Switch Scheduling

• We will simulate with various scheduling
  mechanisms including Multicast schemes.
• iSLIP, RR, FCFS etc
• Virtual Output Queues to avoid HOL
• Nominal Fabric speedup and priority classes.
• Implement both Drop-tail and RED buffer schemes.

9
Switch Fabric

• Shoot for 1024x1024 but backup is 64x64
• Vitesse VSC836 takes too long to configure!!
• Use AMCC S2018 17x17 in a 3-stage CLOS network.
• Other options?

10
Output Port Processing and scheduling

• Basic de-framing and physical level processing.
• FQ discipline
• WFQ
• W2FQ
• How do we do this with input buffering?

11
Plan of Action

• Decide on IPP and Network Processor.
• Concentrate on switch fabric choice.
• Analyze switch scheduling schemes.
• Try to implement FQ with input port buffers.
• Implement RED and Drop Tail.
• Develop a simulator for the switch.
• Experimentally determine the buffer size.