FEV And Netlists

1
FEV And Netlists

• Erik Seligman
• CS 510, Lecture 5, January 2009

2
Goals

• Review how logic changes in synthesis
• Understand how to make RTL-netlist FEV work
• Mainly looking at synthesized netlists
• Grab Bag of cool techniques for FEV
• Look at interesting corner cases

3
Synthesized Netlist Basics

• Synthesized netlists built from cell library
• Cells hide transistor-level logic
• Delivered with behavioral descriptions
• Library owners certify correctness
• Be sure you have a library!
• FEVing full block at transistor level is
  expensive
• Cell and custom FEV is separate process

4
Custom Cell FEV

• Typically done by specialized team
• FEV tools like have special functionality
• LEC custom
• abstract logic
• Users have to give many hints to tool
• Transistor, pin directions
• Which nodes are meant to hold state
• Domino precharge nodes

5
State Negation And Replication
6
Are these equivalent?
a
f1
f2
b
out
ck
a
f3
f4
out
b
ck
7
Yes- State Negation is OK
a
f1
f2
b
out
ck
a
f3
f4
out
b
ck
add mapped point f2 f4 inv OR set mapping method
-phase
8
Are these equivalent?
a
f2
b
out
ck
a
f2_1
b
out
ck
f2_2
9
Yes- State Replication
a
f2
b
out
ck
a
f2_1
b
out
ck
f2_2
add instance equivalence f2_1 f2_2 rev
10
Dont Forget Key Point Mapping (One
Representative)
a
f2
b
out
ck
a
f2_1
b
out
ck
f2_2
add instance equivalence f2_1 f2_2 rev add
renaming rule r1 f2 f2_1 -gold
11
Pin Replication Also Common
a
f2
b
out
ck
a
f2_1
b
out
ck1
f2_2
ck2
add pin equivalence ck1 ck2 rev add renaming
rule r2 ck ck1 -gold
12
Scan Chains and FEV
13
What Is A Scan Chain?

• Enable observation of internal states
• Critical for post-silicon debug
• May enable setting internal states as well
• May involve all (full scan) or some states
• Do this by creating serial chain
• Minimize need for additional pins
• Cost Extra wires more complex flops

14
Logic Example (no scan)
f1
f2
a
out1
ck
f3
f4
out2
b
ck
15
Logic Scan Chain
sen
si
f1
f2
a
out1
ck
so
f3
f4
b
out2
ck
16
Handling scan chains in FEV

• Be careful! Scan in netlists, but not RTL
• Scan insertion is during synthesis
• Identify scan enable conditions
• May be simple scan enable pin
• Or combination of pins / states
• Use FEV constraints to disable in netlist
• add pin constraint 0 scan_en rev
• Plan to address verification hole!
• Gate-level simulation of netlist
• Or custom scripts to walk chains

17
Clock Gating
18
What is Clock Gating?

• Goal Power Reduction
• Stop clock to inactive flops
• No clock change ? No switching power
• Automatically inserted in synthesis
• Thus in netlist but not RTL

19
Enabled Flop (no clk gating)
en
ff
a
out
ck
20
Enabled Flop Clock Gating
a
ff
out
ck
en
DLAT
set flatten model gated_clock
21
Black Boxes
22
What is a Black Box?

• Area of logic to ignore for FEV
• Usually a Verilog module instance
• Why ignore some logic?
• Non-FEVable analog circuits
• Hard IP externally supplied block you trust
• Divide conquer different ownership
• What is verified?
• Drivers of bbox input pins
• Recipients of bbox outputs
• Internals are ignored be careful!

23
Black Box Example
TOP
YELLOW
a
c
b
add black box /top/yellow both
24
Black Box Example
TOP
YELLOW
a
c
b

• TOP.YELLOW is a single key point
• But mapped only if a, b, and c have matches
• Verify fails if logic driving a or b mismatches

25
Dont Care (DC) Space
26
Are these equal?
a
or
b
a
xor
b
27
What if we see source RTL
a
or
out
b
a
xor
out
b
case (a,b) 2b00 out0 2b01 out1
2b10 out1 endcase
28
What if we see source RTL
a
or
out
b
a
xor
out
b
case (a,b) 2b00 out0 2b01 out1
2b10 out1 endcase
Unspecified case is a Dont-Care (DC)
29
Dont Care Cases

• Often result from underspecified RTL
• Synthesis has freedom to choose values
• Can optimize for area, timing, etc.
• FEV tools can handle automatically
• BUT DCs only come from GOLD model
• DC in REV model is an error (E)
• Asymmetry between GOLD and REV!

30
Watch out for confusion!
RTL
FEV-clean
FEV-clean
Netlist1
Netlist2
FEV mismatches
31
Pipeline Retiming
32
Are these equivalent?
f3
a
out
b
f2
a
out
b
f1
33
Are these equivalent?
f3
a
out
b
f2
a
out
b
f1

• Yes, in a sequential sense.
• Logic moved across flop Pipeline Retiming

34
Pipeline Retiming and FEV

• Retiming violates state matching
• Shouldnt expect combo FEV tool to handle
• BUT recent tools can handle some cases
• FEV tools aware of synthesis techniques
• Internally push logic along pipeline to match
• add module attribute m1 pipeline_retime
• Many limitations, be careful
• Retiming must be isolated to one module
• Can cause runtime/memory complexity
• Need sequential FEV for more general cases

35
References / Further Reading

• Scan
• http//en.wikipedia.org/wiki/Scan_chain
• http//web.cecs.pdx.edu/greenwd/ch03art.pdf
• Clock Gating
• http//www.eng.auburn.edu/vagrawal/COURSE/E6270_F
  all07/PROJECT/LUO/snug2000.pdf
• http//www.chipdesignmag.com/display.php?articleId
  915
• Pipeline Retiming
• http//www.cdnusers.org/community/encounter/resour
  ces/resources_imp/verif/Dtp_cdnlive2005_1207_Emban
  ath.pdf
• http//www.cdnusers.org/Portals/0/cdnlive/na2006/2
  .3/2.3_paper.pdf