Total Dose and SEE of Metal-To-Metal Antifuse FPGA

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Total Dose and SEE of Metal-To-Metal Antifuse FPGA
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Outline

• 1. Introduction to M2M antifuse FPGA
• 2. Total Ionizing Dose
• 3. Single Event Effects
• SEU
• SEL
• SEDR
• 4. Summary

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RT54SX

• 16k, 32k, 72k gate antifuse FPGA
• 0.6mm (3.3/5.0V), 0.25mm (2.5/3.3/5.0V) CMOS
  technology
• Commercial foundry

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Sea-of-Module Architecture
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Sea-of-Module Architecture
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Basic Logic Modules
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M2M Antifuse
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SX Pin-to-Pin Performance

• Fast, Flexible Array Logic and Routing
• Fast pin-to-pin timing

Input
TPD 0.6ns
TIRD1 0.3ns
Array C-Cells
TFC 0.3ns
TINYH/INYL 1.5ns
TPD 0.6ns
TFC 0.3ns
TPD 0.6ns
Output
TRD1 0.3ns
TDLH/DHL 1.6ns
6.1ns
Total Pin-to-Pin Timing, 32-bit Decode
Numbers shown for A54SX16-3, worst case
commercial conditions
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RTSX TID

• 0.6mm
• Tolerance limited by static ICC
• 100krad(Si)
• 0.25mm
• Tolerance limited by static ICC
• Shallow trench isolation
• 65krad(Si) before improvement, 250krad(Si) after
  improvement

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0.6mm RTSX TID
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0.6mm RTSX TID (Proton)
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0.25mm RTSX TID
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0.6mm RTSX SEU
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User Level SEU Hardening
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0.25mm RTSX SEU
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SEU-Hard TMR Flip-Flop
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Single Strike Double Upset in SEU Hard FF
Simulated by using Space Rad 4.0, Multiple-Bit
Upset module
Active Junction in FF1
Active Junction in FF2
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Single Event Latchup

• RT54SX is latchup immune,
• i.e., LETth gt120MeV-cm2/mg

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Single Event Dielectric Rupture
E-fieldM2M 3.3V/700A 0.5MV/cm E-fieldONO 5V/10
0A 5MV/cm

• Antifuse structure 1 Both 0.6mm and 0.25mm are
  immune to SEDR.
• Antifuse structure 2 0.6mm
• Original structure has LETth40MeV-cm2/mg at
  VCC3.3V.
• New recipe is immune (no rupture at right angle
  incidence, LET60MeV-cm2/mg, VCCgt3.6V).

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SUMMARY

• TID
• RTSX has good tolerance, 50k-100krad(Si).
• Smaller geometry shows potential for higher
  tolerance.
• SEU
• 0.6mm RTSX shows better tolerance than ACT2, ACT3
  (ONO).
• FF LETth SX11, ACT2/34
• CC LETth SXgt40, ACT2/320
• 0.25mm RTSX have hardened FF option.
• SEL
• RT/RHSX are immune.
• SEDR
• RT/RHSX are immune.