Transactional%20Memory%20Overview

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Transactional Memory Overview

• Olatunji Ruwase
• 15-740 Fall 2007
• Oct 4 2007

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Future PCs are Multicore
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Parallel s/w for performance

• Locks
• Deadlocks
• Priority Inversion
• Buggy
• Convoy Effect
• Limited concurrency

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Transactions

• Borrowed from Databases
• Definition A transaction is a finite sequence
  of machine instructions executed by a single
  process, that satisfies the following properties
• Atomicity
• Serializability

Herlihy and Moss. Transactional Memory
Architectural Support for Lock-free Data
Structures, ISCA93
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How transactions work

• Make private copy of shared data
• Make updates on private copy
• If shared data is unchanged
• Update shared data with private copy
• Else conflict has occurred
• Discard private copy and repeat transaction

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Requirements for supporting transactions

• Buffering
• Conflict detection
• Abort/Rollback
• Commit

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Transactional Memory

• Herlihy and Moss, ISCA 93
• ISA changes
• LT,LTX, ST, COMMIT, VALIDATE, ABORT
• Fully associative transactional cache
• Per processor
• Contents are exclusive of regular cache
• Cache coherence protocol changes
• Transactional cache line states
• Transactional bus messages
• Snoopy bus based implementation

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TM support for transactions
Buffering Transactional cache
Conflict detection Cache coherence protocol
Abort/Recovery Invalidate transactional cache line
Commit Validate transactional cache line
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Transactional Cache

• Fully set associative cache
• Each cache line can be in only one of
  transactional or regular cache
• Holds transactional writes
• Transactional writes are hidden from other
  processors and memory
• Makes updated lines available for snooping on
  COMMIT
• Invalidate updated line on ABORT

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Herlihy and Moss, ISCA 93
Memory
M
S
S
XCommit
XAbort
Cache
Transaction Cache
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Sample Counter code
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Exposing more concurrency

• Doubly linked list implementation of queue
• Head, Tail pointers
• If queue not empty
• Only head pointer is used for dequeuing
• Only tail pointer is used for enqueuing
• Concurrent enqueuing/dequeuing
• Possible in TM
• Not possible with locks

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Challenges of TM

• Long transactions
• I/O
• Nested transactions
• Interrupts

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Other TM Ideas

• Speculative Lock Elision
• Software Transactional Memory
• Requires no hardware changes
• Allows composition of transactions

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Speculative Lock ElisionRavi and Goodman, MICRO
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• Speculatively remove lock acquire and removal
  instructions
• Microarchitectural changes
• No changes to cache systems
• No changes to ISA
• Can work with existing lock based code

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SLE example
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Credits for slides

• Bryant Lee (CMU)
• Transactional Memory Principles and Current
  Research
• Colin Blundell (UPenn)
• Transaction Memory Overview
• Kevin Moore (UW)
• Thread-Level Transactional Memory

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Compare TM and TLS

• TM is optimistic synchronization
• TLS is optimistic parallelization
• Any other similarities or differences

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Questions/Discussions