Finite State Machines part I

1
Finite State Machinespart I

• Lecture 06

2
Synchronous Circuits

• Consider an arbitrary digital circuit that has
  the following two constraints.
• Every flip-flop shares a single clock signal
• Every part of the circuit that contains only
  simple gates cannot contain loops.

3
Finite State Machines
Most circuits have the following structure.
There are two combinational circuits and a
register thus the circuit can be uniquely
specified by simply writing TWO truth tables, one
for the IFL and the other for the OFL.
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Circuit States
To design Finite State Machines we begin by
drawing a state diagram that describes our
desired circuit behaviour. We can write the two
truth tables once we have the state diagram. Then
we simplify and draw the circuit.
The concept is simple. Combinational circuits are
circuits whereby, at any instant, the circuit
outputs respond to the circuit inputs at that
same instant. The circuits behaviour is only
dependent on the NOW.
In many cases a circuit output will depend not
only upon the CURRENT inputs but also upon the
behaviour of the circuit in the PAST. For
Example, a tape recorder has buttons, PLAY, STOP,
PAUSE, REW, FWD. These are the circuit inputs.
The machine controls a motor (ON/OFF), the
direction of the motor (F/R), and engages a
magnetic head onto the tape (ON/OFF). These are
the circuit outputs. Consider this. If you
momentarily push PLAY and then PAUSE, the head in
engaged on the tape. BUT if you momentarily push
STOP and then PAUSE the head in not engaged.
Clearly the action of the PAUSE button alone is
not enough to decide whether to engage the head.
The circuit needs to remember information about
its past inputs and thus has flip-flops to store
this information. The flip-flops store a code
that represents the state of the system.
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State Diagrams
If there system has N inputs, M outputs and
K-bits in the state register then, The IFL and
OFL truth tables will have 2(NK) rows. The
system has 2K possible states and thus the rows
of the truth table can be grouped by state. Each
state will have 2N combinations for the inputs.
We represent the states of the system by drawing
a circle with the state code in the center. We
represent the rows of the truth tables by drawing
arrows EXITING the states. Every state must have
exactly 2N arrow exiting. We label the arrows
with the input combinations.

• We label the arrows with any circuit outputs that
  we choose.
• We connect the head of the arrows to any state
  that we choose.
• This is equivalent to choosing the Right Hand
  Side values in the IFL and OFL truth tables.

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Sequence Detection
Let us design a circuit that has only a single
input, called x and a single output called y.
Suppose that the bits stream on x changes with
the clock. We wish to activate y for a single
cycle whenever the sequence 1101 occurs.
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Forming The State Diagram

• There are 4 states thus 2-bits in the state
  register.
• There is 1 input thus the IFL and OFL truth
  tables will have 8 rows.
• Check that you have 8 arrows.

Now we need to fill in the missing arrows. Every
state must have two arrows exiting.
Finally, you add the values for the OFL truth
table outputs.
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Arbitration
Lets do another simple example. This time well
consider a circuit with TWO inputs.
Suppose we have a class with 2 students called A
and B. The teacher asks a question every 5
seconds. The students raise their hands to
request permission to answer the question. The
teacher then grants permission to answer the
question by pointing his hand toward the chosen
student. This teachers decision is simple when
only one student raises a hand. The problem
arises when both students wish to answer a
question. Which student does the teacher choose?
The Teacher must record information about the
past inputs. The teacher notes that there are TWO
possible states. A has priority and B has
priority. The teacher remembers which state he in
and uses his state information as well as the
students hands when deciding which student to
select or not.
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Arbitration State Diagram
First we draw the states.
Now we start adding the arrows. Each state must
have FOUR arrows exiting labeled
Now check that each state has its EXIT arrow
correctly labeled with every possible combination
of the inputs.
Finally you must add the output signals to each
of the arrows. You can choose appropriate outputs
and label the arrows at home.
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Writing Truth Tables for the IFL and OFL
The state diagram contains everything needed to
write the truth tables for both combinational
circuits, IFL and OFL.
The arrows represent the rows of the truth
tables. The OFL outputs are labeled on the arrows
and the arrow heads determine the IFL outputs.
Before completing the IFL table you must decide
whether you are using D-type or JK-type
flip-flops for the state register. The outputs of
the IFL circuit will connect to the D or JK
inputs of the flip-flops. (see the diagram on
slide 3) You must also decide upon specific BIT
patterns to be representative codes for the
states. You can only complete the tables once
these codes are chosen.
Please write the truth tables for the previous
examples using D-type flip-flops. Please write
the truth tables for the previous examples using
JK-type flip-flops.
You will be required to simulate and synthesize
these two examples as part of assignment1.