Synchronous Methodology for Hardware, Software, and Mixed Embedded Systems

1
Synchronous Methodology for Hardware, Software,
and Mixed Embedded Systems
Part 2 designing in Esterel v7
Gérard Berry
Chief Scientist www.esterel-technologies.com G
erard.Berry_at_esterel-technologies.com
2
Agenda - Part 2Designing in Esterel v7

• The Esterel principle Write Things Once
• Pure signals and basic control
• General signals and datapath equations
• Program units
• Esterel v7 examples
• Comparison with HDLs

3
Agenda - Part 2The Esterel Language

• The Esterel principle Write Things Once
• Pure signals and basic control
• General signals and datapath equations
• Program units
• Esterel v7 examples
• Comparison with HDLs

4
Imperative specification
Emit O as soon has A and B have arrived. Reset
behavior each R
R?
R?
A?
B?
R?
R?
A? B? O!
A? O!
B? O!
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Imperative specification
multiple copies gt explosion
R?
R?
A?
B?
R?
R?
A? B? O!
A? O!
B? O!
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The key idea Write Things Once
loop await A await B emit
O each R

• concurrency
• sequencing
• preemption
• full orthogonality

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The key idea Write Things Once
loop await A await B emit
O each R

• concurrency
• sequencing
• preemption
• full orthogonality

9
N-way Concurrency
loop await A await B await C
emit O each R
scales linearly vs. exponential automata blowup
10
SyncCharts (C. André)Synchronous Hierarchical
Automata
Esterel synchronous semantics
11
Agenda - Part 2The Esterel Language

• The Esterel principle Write Things Once
• Pure signals and basic control
• General signals and datapath equations
• Program units
• Esterel v7 examples
• Comparison with HDLs

12
Standard (Mealy) pure signals
input I output O signal S in ... end

• Emitted and received in the same cycle
  (broadcast)
• signal present if and only if emitted (default
  absent)
• pre(S) operator yields status at previous cycle
• gt sequential expressions
• Multiple drivers allowed

emit S if I and not pre(I) then ... // rising
edge
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Basic control and expressions

• Sequential control flow
• pause
• await S
• every S do p end

• Signal emission
• emit S
• sustain S

• Combinational control flow
• sequence
• concurrency
• abort p when S
• if S then p else q end
• loop p end

• Sequential expressions
• if pre(S)
• await S and not pre(S)

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Sequencing
emit A emit B pause emit C
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Sequencing
emit A emit B pause emit C
A
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Sequencing
emit A emit B pause emit C
A
B
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Sequencing
wait for a cycle
emit A emit B pause emit C
A
B
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Sequencing
emit A emit B pause emit C
C
A
B
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Looping
loop emit A emit B pause emit C end loop
C
A
B
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Looping
loop emit A emit B pause emit C end loop
C
A
B
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Looping
loop emit A emit B pause emit C end loop
C
A
B
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Looping
loop emit A emit B pause emit C end loop
C A
A
B
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Looping
loop emit A emit B pause emit C end loop

• Loop back in the same cycle
• Non-instantaneous body
• Loop invariant cannot reenter if the body still
  executes

C A B
A
B
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Decision
emit A emit B pause loop if C then
emit D else emit Q end if if pre(E) then
emit F end if pause end loop
C
C
E
E
D
D
Q
A
F
F
B
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Concurrency
await A emit C await B emit D
emit E
A
B
D E
C

• Start parallel statements in the same cycle
• Terminate parallel block once all branches
  terminated

B
A
C E
D
A
B
C
D
E
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Preemption
abort pause pause emit A when B emit
C

• Normal termination
• Aborted termination
• Aborted termination emit A preempted

A C
B
C
B
C
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When to react?
await A emit B
await immediate A emit B
A
A
A
B
B
A
A
A
B
B

• Non-immediate (default) form does not react to
  signals arrived during the initial instance
  (before the first tick)

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When to kill?
abort pause emit A pause emit B when
C emit D
weak abort pause emit A pause emit
B when C emit D
C
C
A D
D
C
C
B D
D
A
A

• Strong abort (default) kills all emissions during
  the abort cycle
• Weak abort gives signal emissions the last will

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Four (react, kill) possibilities
when to react to S
weak abort p when S
abort p when S
next
abort p when immediate S
weak abort p when immediate S
now
when to kill P
next
now
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The Esterel Runner
abort loop abort run Slowly when
100 Meter abort every
Step do run Jump run
Breathe end every when
15 Second run FullSpeed each
Lap when 2 Lap
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trap HeartAttack in every Morning do
abort loop
abort run Slowly when 100 Meter
abort every Step
do run Jump run
Breathe ltCheckHeartgt
end every when 15 Second
run FullSpeed each
Lap when 2 Lap end every handle
HeartAttack do run RushToHospital end trap
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Programs mean what they say
module SPEED computes exact speed input
Centimeter, Second output Speed integer loop
var Distance 0 integer in
abort every Centimeter do
Distance Distance 1
end every when Second emit
Speed(Distance) end var end loop end module
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module REGUL function Regfun (integer,
integer) integer input Centimeter,
Second input value GasPedal integer output
Regul integer signal Speed integer in
run SPEED await Speed
sustain Regul (Regfun(?Speed,
?GasPedal)) end signal end module
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abort sustain DmaReq when DmaOk abort
abort every ByteIn do
emit ByteOut (?ByteIn) end every
when DmaEnd when 10 times MilliSecond do
emit TimeOut end abort
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abort sustain DmaReq when DmaOk abort trap
ParityError in abort
every ByteIn do emit
ByteOut (?ByteIn) end every
every 4
ByteIn do if BadParity
(?ByteIn) then exit ParityError end
end every when DmaEnd handle
ParityError do ...... end
trap when 10 MilliSecond do emit TimeOut end
abort
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Programming Concepts Summary

• Signals to communicate with the environment or
  within the program
• Expressions are sequential because of pre
• Control is explicit and sequential
• Waiting and preemption statements give behavior
  desctiption power

no need to separate combinational and
sequential part
37
Agenda - Part 2The Esterel Language

• The Esterel principle Write Things Once
• Pure signals and basic control
• General signals and datapath equations
• Program units
• Esterel v7 examples
• Comparison with HDLs

38
Extensions in Esterel v7 language
Goal remove the current limitations of Esterel
v5 much more expressive, but very same semantics

• Mix of Esterel imperative and Lustre equational
  styles
• Better modularity, (mild) object orientation
• data, interface, and module units
• data and interface inheritance
• Structured ports, arrays, more signal kinds
• value, temp, registered, etc.
• Static code replication (for ... dopar)
• Support for Moore machines
• Numerical encodings
• binary, onehot, Gray, etc.
• 100 synthesizable to RTL/C/System-C, modular
  optimization

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Signal arrays
input I 10 output O N signal S 256 in ...
end

• Composed of independent individual components
• Si yields status at current cycle for
  component i
• pre(Si) yields status at previous cycle

emit Si if Si then ... if pre(Si) then
... emit O lt I and S // pointwise extension
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Registered (Moore) pure signals
output O reg signal S 10 reg1 in ... end

• Emitted at one cycle and and received in the
  next cycle
• S yields status at current cycle,
• next(S) yields status at next cycle
• gt sequential expressions
• Initial status 0 for reg, 1 for reg1

emit next S if S then ... if next(S3) then
...
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Valued signals
input I integer output O integer signal S
10 integer in ... end

• status reactive (not persistent), as for pure
  signal
• value is persistent, ?S returns the value
• value changes only when status present (enable)
• no multiple emitters by default

emit ?S lt 2 if S then emit O(?S1)
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Combined valued signals
output O 10 integer combine signal S
integer combine in ... end

• mutiple emitters allowed
• combination function combines emitted values

signal S integer combine in emit
?S lt 2 emit ?S lt 3 end
signal emit ?O1(?S1)
// ?O1 (23)1 6
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Advanced Signals

output O reg integer //
Moore valued output O reg integer combine
// combined Moore valued output O 10 value
integer // value-only,
persistent output O temp integer
// temporary, non-persistent
Allow fine-grain control over hardware
implementation in particular register allocation
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Data-path equations
emit A1, B lt I or I if (?I gt 0)
?X lt 2 if B next ?Y2 lt pre(?X) 1 if B
and not pre(B)

• equations are concurrent and unordered
• dependencies must be combinationally acyclic
• semantics solution (no delta-cycles, etc)

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Agenda - Part 2The Esterel Language

• The Esterel principle Write Things Once
• Pure signals and basic control
• General signals and datapath equations
• Program units
• Esterel v7 examples
• Comparison with HDLs

46
Data units

• data units defined host data objects and
  parameters
• data units are generic and extensible

data D1 constant N integer 4 type
Time // host (defined in
host language constant Noon Time //
host end data data D2 extends D1
// inherits all objects from D1
function Next (Time) Time // host end data
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Interfaces

• Group logically related signals
• Can be extended and mirrored

interface Intf1 input I, J end
interface interface Intf2 extends Intf1
// imports I, J output O end interface module
M extends mirror Intf2 // input O, output
I,J
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Ports

• A port is a group of signals typed by an
  interface
• Component accessed through dot notation

module M port P Intf2 if pre(P.O) then
emit P.I end end module
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Modules

• A module has an interface and an executable
  behavior
• It can extend interfaces and data units and
  declare
• local objects
• It can be instantiated in another module

module M extends data D extends interface
Intf1 extends mirror interface Intf2 port P
Intf3 every P.Reset do ... end every
... run SubModconstant 4 / N, X / I, Y /
O end module
50
Agenda - Part 2The Esterel Language

• The Esterel principle Write Things Once
• Pure signals and basic control
• General signals and datapath equations
• Program units
• Esterel v7 examples
• Comparison with HDLs

51
Dual-port memory interface
data MemData type T
// generic constant Size
integer 4 end data interface MemWriteIntf
extends data MemData input WriteAddress
integer // address bus input DataIn
value T // data bus end
interface interface MemReadIntf extends
data MemData input ReadAddress integer
// address bus output DataOut value T
// data bus end interface
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Port-based memory interface, 2 ports
interface DualMemIntf port WritePort
MemWriteIntf port ReadPort MemReadIntf end
interface
Extension-based memory interface, 4 signals
interface DualMemIntf extends interface
WriteIntf extends interface ReadIntf end
interface
(MemData automatically imported in both cases)
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The dual memory module
module DualMem extends interface
DualMemIntf signal MemArray MemSize T in
every ReadAddress do emit ?DataOut
?MemArray ?ReadAddress end every every
WriteAddress do emit ?MemArray
?WriteAddress ?DataIn end every
sustain assert CollisionError not ((ReadAddress
and WriteAddress)
and (?ReadAddress
?WriteAddress)) end signal end module
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Fifo11 specification

• One read port and one write port acting
  concurrently
• Bypass from write to read if fifo empty
• Uses a circular buffer in memory, the memory
• having concurrent read / write ports

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include "fifo_data.strl" include
"dualmem.strl" include "fifo11_ctrl.strl" module
Fifo11 extends data MemData input
Write T input Read output DataOut
value T output Empty, Full output
EmptyError, FullError signal WriteAddress,
ReadAddress integer in run Fifo11Ctrl
run DualMem signal Write / DataIn
end signal end module
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// control for the circular fifo with one read
and write port // concurrent write and reads on
an empty fifo lead to bypass module Fifo11Ctrl
extends data MemData input Read
output ReadAddress integer output DataOut
value T input Write T output
WriteAddress integer output Empty
output Full output EmptyError output
FullError signal FifoSize value integer
init 0, DeltaSize temp integer
combine , ReadEmpty, Bypass in
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// compute bypass and error cases
sustain ReadEmpty Read and
pre1(Empty), Bypass ReadEmpty and
Write, Empty (?FifoSize 0),
Full (?FifoSize MemSize), EmptyError
ReadEmpty and not Write, FullError
pre(Full) and Write // compute size
every DeltaSize do emit FifoSize(
pre( ?FifoSize ) ?DeltaSize ) end
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// read section var ReadPointer 0
integer in every case
EmptyError case Bypass do
emit DataOut (?Write ) case Read
do // read from memory
emit ?ReadAddress ReadPointer
ReadPointer (ReadPointer 1) mod
MemSize emit ?DeltaSize lt -1
end every end var // write
section var WritePointer 0 integer in
every Write and not FullError and not Bypass
do emit ?WriteAddress
WritePointer WritePointer
(WritePointer 1) mod MemSize emit
?DeltaSize lt 1 end every end
var end module
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Fifo22 specification

• Two read ports and two write ports, all acting
  concurrently
• Full bypass from write to read from any write
  port to
• any read port according to fifo state and to
• read / write commands
• Uses a circular buffer in memory, the memory
• having two read and two write ports, all acting
  concurrently

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control for the circular fifo with two read and
write ports concurrent write and reads on an
empty fifo lead to bypass module Fifo22Ctrl
extends data FifoData input Read 2
user read command, indexed by port
output DataOut 2 value T user
output, indexed by port input Write 2 T
user write command,
indexed by port output ReadAddress 2
integer memory read addresses, by port
output WriteAddress 2 integer memory
write addresses, by port output Empty 2
0 -gt 0 item at
beginning of cycle
1 -gt 1 item at
beginning of cycle output Full 2
0 -gt MemSize items at beg. of
cycle
1 -gt MemSize-1 items
at beg. of cycle output EmptyError 2
empty errors, by port output
FullError 2 full errors,
by port
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compute empty and full predicates for i lt
2 dopar sustain Full i
(?Entries MemSize - i), Empty i
(?Entries i) end for
compute read and write auxiliaries sustain
ARead Read 0 or Read 1, OneRead
Read 0 xor Read 1, AllRead Read
0 and Read 1, AWrite Write 0 or
Write 1, OneWrite Write 0 xor Write
1, AllWrite Write 0 and Write 1,
Write1Only not Write 0 and Write 1,

62
who reads from empty fifo? always
if Read 0 then emit
ReadEmpty 0 Empty 0,
ReadEmpty 1 Empty 1 and Read 1
else emit ReadEmpty 1
Empty 0 and Read 1 end if end
always
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Full errors, different if no read or one
read always if case not
(ARead) do emit
FullError 0 Full 0 and Write 0,
FullError 1 (Full 0 and Write
1) or (Full 1 and AllWrite)
case OneRead do emit
FullError 1 Full 0 and AllWrite end
if end always Empty errors, different
if no write or one write always if
case not(AWrite) do emit
EmptyError 0 Empty 0 and
Read 0, EmptyError 1
(Empty 0 and Read 1) or (Empty 1 and
AllRead) case
OneWrite do emit EmptyError 1
Empty 0 and AllRead end if end always
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Parametric architectural design
Aa
Unit0
Oa
A
Unit1
O
Unit2
B
Unit3
Ba
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main module Dopar extends data Data input
A, Aa value integer input B, Ba value
integer input Oa value integer output O
output Done signal AdN, BdN, OdN in
sustain Ad?Aa A, Bd?Ba
B, O Od?Oa for i lt
N dopar run Unit signal Adi / A, Bdi
/ B, Odi / O end for emit Done
end signal end module
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A CRC Calculator

• A generator polynomial of degree N
• P 10011
• x4 x 1
• A message to protect
• M 1101011011
• x9 x8 x6 x4 x3 x 1
• Compute the remainder of M after appending N
  zeros by P
• R

• The frame to transmit is M after appending R
• T 2N ?M R
• P?Q R R
• P?Q
• !! T is divisible by P !!

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• Choose a generator polynomial of degree N
• CRC generation
• Append N zeros to the message and compute the
  remainder of the division by the polynomial.
• The frame to transmit is the message after
  appending the remainder.
• CRC check
• The remainder of the division of the frame by the
• polynomial should be null.

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Shift input stream by N ticks
module Shifter constant N integer input
In output Out signal AuxN in sustain
Aux0 lt In, Aux1..N-1 lt
pre(Aux0..N-2), Out lt pre(AuxN-1)
end signal end module
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Serializes a parallel input array and terminates
module TerminatingParallelToSerial constant N
integer input ParallelN output Serial signal
ShifterN in emit Shifter lt Parallel
weak abort sustain Serial lt
ShifterN-1 every tick do //
initial delay emit Shifter1..N-1 lt
pre(Shifter0..N-2) end every when
N-1 tick end signal end module
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Remainder calculation
R0
R1
RN-1
Divided
Divider0
Divider1
DividerN-1
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Compute the remainder of the input stream by a
divisor
module RemainderComputer constant DivisorDegree
integer input DivisorDivisorDegree input
Dividend output RemainderDivisorDegree
reg sustain next Remainder0 Dividend
xor
(Divisor0 and RemainderDivisorDegree-1),
for i lt DivisorDegree-1 do next
Remainderi1 Remainderi
xor (Divisori1 and
RemainderDivisorDegree-1) end for end
module
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Compute current CRC at each tick
module CRCComputer constant Degree
integer input DataIn output CRCOutDegree
reg signal DivisorDegree in run
DivisorSustainer // should sustain divisor
coefficients run RemainderComputer
constant Degree / DivisorDegree
signal Divisor /
Divisor,
DataIn / Dividend,
CRCOut
/ Remainder end signal end module
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CRC encoder
0
Message
In
Out
Message
CRC
Latency CRC length
74
CRC encode
module CRCEncoder constant CRCLength
integer constant MessageLength integer input
DataIn output DataOut signal CRCComputerIn,
CRCCRCLength in abort sustain
CRCComputerIn lt DataIn run CRCComputer
constant CRCLength / Degree
CRCComputerIn / DataIn, CRC /
CRCOut run Shifter constant CRCLength
/ N DataIn / In, DataOut
/ Out when MessageLength CRCLength tick //
CRC now available, transmit it run
TerminatingParallelToSerial constant CRCLength /
N
CRC / Parallel, DataOut / Serial end
signal
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CRC encode or CRC check
module CRCEncoderChecker extends
CRCEncoder input Check // if false, encode,
if true, decode and flag errors output
CRCError run CRCEncoder if Check then
await MessageLength tick abort
sustain CRCError lt DataOut when
CRCLength tick end if end module
76
CRC Testbench
0
Message
In
Message
CRC
Message
0 expected
77
Testbench divisor
data CRC_10_4_Data constant CheckCRCLength
integer 4 constant CheckMessageLength
integer 10 // in bits end data module
DivisorSustainer // x4x1 extends
CRC_10_4_Data output DivisorCheckCRCLength sus
tain Divisor0, Divisor1, end module
78
Testbench
module CRC_10_4_Testbench extends
CRC_10_4_Data input MessageCheckMessageLength
input InjectError output DataOut // the
data out of the normal CRC
// latency CheckCRCLlength,
// length CheckMessageLength
CheckCRCLength output CheckDataOut // the data
out of the CRC checker
// latency 2CheckCRCLlength,
// length
CheckMessageLength CheckCRCLength // comment
the following input relation to build a
counter-example input relation not InjectError
// set InjectError always absent
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signal LocalMessageCheckMessageLength, DataIn
in // keep message in local emit LocalMessage
Message every tick do emit
LocalMessage pre(LocalMessage) end every
// CRC generation from initial message trap
EndCRCGeneration in // run ParallelToSerial
on message, terminates after N tick run
TerminatingParallelToSerial constant
CheckMessageLength / N
LocalMessage /
Parallel, DataIn / Serial // stay silent
(0) on DataIn for CRCLength ticks, wait CRCLength
latency await (CheckMessageLength
2CheckCRCLength) tick exit
EndCRCGeneration // pass data bit to
CRC generator run GenerateCRC / CRCEncoder
constant CheckCRCLength / CRCLength,

CheckMessageLength / MessageLength

// implicit DataIn and DataOut end trap
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// CRC generation from encoded message
// skip initial latency before starting check
await CheckCRCLength tick signal CheckDataIn
in sustain CheckDataIn lt DataOut xor
InjectError // pass data out bits
from message encoder to a new CRC generator
run GenerateCRC / CRCEncoder constant
CheckCRCLength / CRCLength,

CheckMessageLength / MessageLength

CheckDataIn / DataIn,
CheckDataOut /
DataOut // skip message part
await CheckMessageLength CheckCRCLength tick
abort sustain assert OK not
CheckDataOut when CheckCRCLength tick
end signal end signal end module
81
Graphical Programming

• Hierarchical state machines, concurrency /
  preemption
• Data path equations inside states
• 100 compatible with textual programming

gt often more readable, animation easier to
follow (see demos)
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Agenda - Part 2The Esterel Language

• The Esterel principle Write Things Once
• Pure signals and basic control
• General signals and datapath equations
• Esterel v7 examples
• Comparison with HDLs

84
Esterel more concise than Verilog
loop await case icu_miss do
if not cacheable then await
normal_ack or error_ack else
abort await 4 times normal_ack
when error_ack end
end case pcsu_powedown and not jmp_e
and not valid_diag_window do
await pcsu_powerdown and not jmp_e
end end pause end loop
Example from S. Edwards
85
Esterel more concise than Verilog
Write to memory as soon as Addr and Data have
arrived. Wait for memory Latency before
iterating. Restart behavior each Replay.
86
Esterel more concise than Verilog
Write to memory as soon as Addr and Data have
arrived.
Verilog explicit FSM
Esterel write things once
await Addr await Data emit
?Write lt funcW(?Addr,?Data)
A
D
A, D / W()
A / W()
D / W()
87
Esterel more concise than Verilog
Write to memory as soon as Addr and Data have
arrived. Wait for memory Latency before
iterating.
Esterel write things once
Verilog explicit FSM
loop await Addr await Data
emit ?Write lt funcW(?Addr,?Data)) await
Latency times tick end loop
A
D
A, D / W()
A / W()
D / W()
L0
X L-1
X 0
X gt 0 / XX-1
88
Esterel more concise than Verilog
Write to memory as soon as Addr and Data have
arrived. Wait for memory Latency before
iterating. Restart behavior each Replay.
Verilog explicit FSM
Esterel write things once
R
loop abort await Addr await Data
emit ?Write funcW(?Addr,?Data) await
Latency times tick when Replay end loop
R
A
D
R
A, D / W()
A / W()
D / W()
L0 or R
X L-1
X 0 or R
X gt 0 / XX-1