Title: Chap 8. Sequencing and Control
1Chap 8. Sequencing and Control
28.1 Introduction
- Binary information in a digital computer
- data
- manipulated in a datapath with ALUs, registers,
multiplexers, and buses - control
- provide signals that activate the various
microoperations determine the sequence in which
the various actions are performs - Synchronous digital system
- Achieve synchronism by a master clock generator
- Control unit
- Generates binary variables that control the
selection inputs of multiplexers, buses, ALUs,
load control inputs of registers
38.1 Introduction
- Control unit
- a sequential circuit with state that dictate the
control signals for the system - using status conditions and control inputs, the
sequential control unit determines the next
state, in which additional microoperations are
activated - 2 distinct types of control units
- For programmable system
- For nonprogrammable system
48.1 Introduction
- Programmable system
- Input a sequence of instructions
- Instructions specify the operations the system is
to perform - instructions are stored in memory (RAM or ROM)
- program counter (PC)
- provide the address in memory of the instructions
to be executed - executing an instruction
- activating the necessary sequence of
microoperations in the datapath that are
required to perform the operation specified by
the instruction - Non-programmable system
- not responsible for obtaining instructions, nor
for sequencing the execution of those
instructions - determines the operation to be performed the
sequence of those operations, based on only its
inputs and the status bits
58.2 Algorithmic State Machines
- Data processing tasks
- register transfer operations controlled by a
sequencing mechanism - can be specified as a hardware algorithm that
consists of a finite number of procedural steps
which perform the data processing task - Flowchart
- a convenient way to specify a sequence of
procedural steps decision paths for an hardware
algorithm - ASM (Algorithmic State Machine)
- describes a sequence of events, as well as the
timing relationship between the states actions - Cf) S/W program S/W algorithm - Flowchart
68.2 Algorithmic State Machines
- ASM Chart Elements
- state box register transfer operations or
output signals - decision box describes the effect of inputs on
the control - conditional output box from decision box
RUN
78.2 Algorithmic State Machines
- ASM chart
- State diagram for the sequential circuit part of
the control unit - An ASM block
- One state block
- All of the decision and conditional output boxes
connected between the state box exit and entry
paths to the same or other state boxes.
88.2 Algorithmic State Machines
0
1
Register transfers and state changes both wait
until the next positive clock edge.
98.3 Decision Example Binary Multiplier
- multiplies 2 unsigned binary numbers
Binary Multiplier a copy of the multiplicand is
added to a partial product the partial product
is stored in a register for the shift action the
partial product is shifted to the right (adder
is needed for only n bit positions
instead of 2n bit)
108.3 Decision Example Binary Multiplier
- Hardware Multiplication Example
n-bits
Partial product
Copy of multiplicand
Partial product stored in a register in
preparation for the shift action to follow
118.3 Decision Example Binary Multiplier
- Block Diagram for Binary Multiplier
4
128.3 Decision Example Binary Multiplier
- multiplicand is loaded into register B from IN
- multiplier is loaded into register Q from IN
- partial product is formed in reg A, stored in
reg A Q - C F/F stored the carry Cout shifted into
the MSB of A, - LSB of A is shifted into the MSB of Q, LSB
of Q is discarded - Q0 holds the bit of the multiplier that must be
considered next - counter P
- count the number of add-shift or shift actions
- initially set to n-1 counted down
138.3 Decision Example Binary Multiplier
- ASM Chart for Multiplier
- IDLE
- multiplication process starts when G becomes 1
- (ASM moves from state IDLE to
state MUL0) - MUL0
- a decision is made based on Q0
- MUL1
- a right shift is performed on C, A, Q
- C ? 0, C ?? A ?? Q ? sr C ?? A ?? Q
148.4 Hardwired Control
- 2 distinct aspects to deal with
- control of the microoperations
- part of the control that generates the control
signals - Table 8-1
- sequencing of the control unit microoperations
- part of the control that determines what happens
next - Table 8-2
158.4 Hardwired Control
- Control signals for binary multiplier
- based on the ASM chart
168.4 Hardwired Control
- Sequencing Part of ASM Chart
- information on sequencing is represented with
information on microoperations removed - conditional output boxes are removed
- decision box not affecting the next state is
removed - design the sequencing part of the control unit
with the ASM chart i.e. the part that
represents the next-state behavior
178.4 Hardwired Control
- Sequence Register and Decoder
- provide an output signal corresponding to each of
the states - A register with n F/Fs can have up to 2n
states n-to-2n decoder has up to 2n
outputs, one for each of the states - consist of 3 states and 2 inputs
- ? 2 F/Fs and 2-to-4-line decoder
188.4 Hardwired Control
- state table for the sequencing part
- designate 2 F/Fs as M1 M0
- state 00 (IDLE), 01 (MUL0), 10 (MUL1)
- input equations for F/Fs
- DM0 IDLE G MUL1 Z
- DM1 MUL0
198.4 Hardwired Control
- One Flip-Flip per state
- another possible method of control
logic design - A F/F is assigned to each of the state,
- only one of F/F contains a 1, with others 0
208.4 Hardwired Control
- Control unit with one flip-flop per state
- N f/fs are required.
- Simplicity ? a little design effort
218.7 Microprogrammed Control
- Micro-programmed control
- a control unit with its binary values stored as
words in memory - Micro-instructions
- one or more microinstructions
- Micro-program
- fixed at the time of the system design stored
in ROM
228.7 Microprogrammed Control
- ROM
- Contents of a word in ROM specify the
microoperations to be performed for both the
datapath the control unit - CAR (control address register)
- specifies address of microinstruction
- Sequential circuit Moore type
- CDR (control data register)
- holds the microinstructions currently being
executed by the datapath and the control unit - for pipelining
- CDR holds the present microinstruction while the
next address is being computed the next
microinstruction is being read from memory - Next-address generator
- produce the next address, depending on inputs
(status bits) - Sequencer
- next-address generator combined with CAR
238.7 Microprogrammed Control
CAR Moore-type sequential circuit - not allow
conditional output box
248.7 Microprogrammed Control
- status bits enter the next-address generator
affect the determination of the next state - 4 control signals are needed for the
datapath Initialize, Load, Clear_C, Shift_dec - 4 control signals can be used as given or can be
encoded to reduce the number of bits in
microinstruction - ?? ??, INIT???? ???? control????
258.7 Microprogrammed Control
- a microprogram for the binary multiplier in
register transfer notation - microinstruction corresponds to each of the state
in ASM chart
268.7 Microprogrammed Control
- 3 control signal combinations are used
- (Initialize, Clear_C) in state INIT ? 0101
- (Load) in state ADD ?
0010 - (Clear_C, Shift_dec) in state MUL1 ? 1100
- IDLE, MUL0 ? no control signal ? 0000
- format of the microinstruction control word
- DATAPATH 4-bit code
- NXTADD0, NXTADD1 define the next addresses
based on decision - SEL select whether to make a decision
- if so, to select which one of the three
decision variables G, Q0, Z
278.7 Microprogrammed Control
- For sequencing the control unit
288.7 Microprogrammed Control
- Design a control unit
- length of ROM control words 12 bits
- ROM contains 5 words
- since there are only 5 status
- CAR 3-bit parallel load register
Note) - ROM? ?? - CAR? ?? - NAR? ??
298.7 Microprogrammed Control
- Register transfer micro-program
- symbolic microprogram
Binary representation
30Design of Control Units
- Hardwired control
- For non-programmable system
- Micro-programmed control
- For programmable system
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