ELG 4132 Tutorial Principles

1
ELG 4132 Tutorial Principles Application of
VLSI Design

• VHDL DESIGN
• MULTI-MASTER SYSTEM BUS AND SHARED MEMORY
  COMMUNICATION

2
Presentation Outline

• Overview
• Bus Interconnection
• Bus Structure
• Bus Transaction
• Bus Clocking
• Bus Control
• Example Buses
• Design and Implementation
• Summary

3
Overview

• Bus
• A common electrical pathway connecting multiple
  devices
• Serves as a shared communication link between the
  subsystems

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Bus Interconnection Bus structure
Pentium System Organization

• Processor-memory buses
• Short and high speed
• Connects directly to the processor
• I/O Buses
• Usually lengthy and slower
• Wide range in the data bandwidth
• Backplane Bus
• Allow processors, memory and I/O devices to
  co-exist

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Bus Interconnection Bus transaction

• A typical bus transaction includes two parts
• Issuing the command by sending the address
• Taking the action by transferring the data
• a read transaction transfers data from memory
• a write transaction writes data to the memory.
• The devices that attached to a bus, actively
  starting the bus transactions are called masters
  and the passive ones that responding to the
  masters are called slaves.
• Operational rules must be set to ensure orderly
  data transfers on the bus -- bus protocol.

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Bus Interconnection Bus Clocking

• Synchronous bus has a line driven by a crystal
  oscillator, which includes a clock in the control
  lines.
• Asynchronous bus dose not have master clock,
  which requires a handshaking protocol or
  interlocking mechanism.

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Bus Interconnection Bus Control

• Arbitration-
• In a modern computer system, more than one device
  need control the bus at the same time but, only
  one device can successfully transmit over the bus
  at one time. The process of assigning control of
  the data transfer bus to a requester is called
  arbitration.
• Designing a bus arbitration scheme is one of the
  most important issues in bus design it usually
  try to balance two factors bus priority and
  fairness.
• Example Daisy chain arbitration, Centralized
  parallel arbitration, Decentralized bus
  arbitration, Distributed arbitration.
• ,

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Bus Interconnection Bus Control

• Centralized Parallel Arbitration-
• Multiple bus request / grant signal lines can be
  independently provided for each potential master.
  In this scheme, each device has its own bus
  request / grant line, and the arbitration among
  potential masters is carried out by a central
  arbiter (central arbiter decide).
• Very powerful and used in essentially all
  processor-memory buses and in high-speed I/O
  busses.

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Example Buses

• Historical and current-
• Unibus (PDP-11)
• Multibus (8086)
• VME bus (physical lab)
• ISA bus (PC/AT)
• EISA bus (80386)
• Nubus (macintosh)
• PCI bus (PCs)
• SCSI bus (workstations)
• SOC bus (system on-chip) AMBA (AMD) and Avalon
  (Altera Nios)
• USB bus (modern PCs)
• Fire wire (consumer electronics)

Different buses have different arbitration
policies
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Example Buses (cont)

• Example Buses (SOC bus)-
• Designed for connecting on-chip processors and
  peripherals together into a SystemOnaProgrammab
  le Chip (SOPC)

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Example Buses (cont)

• Example Buses (Traditional vs. Avalon)
• Traditional
• a single arbitrator controls communication
  between multiple bus masters and bus slaves.
  The arbitrator will grant a single master access
  to the bus after each potential master giving
  the control request. If more than one masters
  attempt to access the bus, the arbitrator
  allocates bus resources to a single master based
  on a fixed set of arbitration rules
• Traditional systems have a bandwidth bottleneck
  because only one master can access the system bus
  at a time.

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Example Buses (cont)

• Example Buses (Traditional vs. Avalon)
• Avalon
• The Avalon is simultaneous multi-master bus
  architecture which increases system bandwidth by
  eliminating this bottleneck because bus masters
  contend for individual slaves, not for the bus
  itself.
• In Avalon, multiple masters can be active at the
  same time and can simultaneously transfer data to
  their slaves. Masters do not have to wait to
  access a target slave, as long as another master
  does not access the same slave at the same time.

13
Example Buses (cont)

• Example Buses (Traditional vs. Avalon)
• Avalon
  Traditional

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Lab3 Design

• Objective
• Design a simple multi-master bus system utilizing
  the shared memory message passing techniques and
  establish communication between several bus
  masters collaborating in performing an I/O task.
• Platform
• Nios Development Hardware Board.
• Quartus II software

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Lab3 Design

• Central arbitration with independent requests and
  grants
• Central arbiter carries out arbitration among
  multiple masters, and each master is connected to
  the central arbiter via its own independent bus
  request and grant lines.

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Lab3 Design

• Consider the multi-master system and two bus
  masters (M0 and M1) use message passing through
  shared memory to collaborate in performing an I/O
  task, our task is simplified to lighting the LEDs
  on the Nios board one after the other. However,
  the two masters will collaborate in a round-robin
  fashion in driving the LEDs.

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Lab3 Design

• ? M0 have higher priority and get control of the
  bus
• M0 checks the memory location associated with
  messages from M1 (default value of this location
  should signal M0 to turn on the first LED)
• M0 proceeds by turning on LED0
• It then leaves a message for M1 in the memory and
  give up the control of the bus.
• The arbiter then passes control of the bus to M1
• Checks the message stored in memory from M0 to
  see which LED should be turned on next.
• M1 turns on the next LED (LED1) and leaves a
  message for M0.

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Lab3- Design

• Memory Module Design
• A memory block of two eight-bit words, which
  allows for a read or a write operation every
  clock cycle. Since the memory block consists of
  only two cells, a two-bit address bus should
  suffice to map the system. The Least Significant
  Bit (Address_bus(0)) of the address bus will
  decode which memory cell is to be accessed, and
  the Most Significant Bit (Address_bus(1)) of the
  bus will be used to choose between the memory
  block and the I/O buffer.

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Lab3-Design (Memory Module)
process(clk) beg
in if(rising_edge(clk))
then if(reset '1') then mem0 lt
"11111110" mem1 lt "11111101" el
sif(readEn '1') then
if(address_bus(0) '0') then data_out lt
mem0 elsif(address_bus(0) '1')
then data_out lt mem1 end
if elsif(writeEn '1') then
if(address_bus(0) '0') then mem0 lt
data_in else mem1 lt
data_in end if else
data_out lt "ZZZZZZZZ" end if
end if end process
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Lab3-Design (Bus Master)

• State diagram
• On reset, each master will initialize its Bus
• Request (BR) signal to logic low. In waiting-
• for-bus state BR is set high to
• issue a bus request signal to the arbiter, and
• the master waits for Bus Grant (BG) to arrive.
• Once the BG signal is issued by the arbiter,
• the master enters a memory-read state to
• read the message stored in the memory from the
  other master module.
• Next, based on the read message, the master
  drives the I/O register. In
• the next state, a memory-write operation is
  performed to leave a message
• for the other master. Finally, a transition is
  made back to the initial state.

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Lab3-Design (Bus Master)
Which memory Cell?

• M0.vhd

when memory_read gt BR lt
'1' address lt "00" readmem lt
'1' writemem lt '0' data_out lt
"ZZZZZZZZ" message data_in next_state
lt to_IO when to_IO gt BR lt
'1' address lt "10" readmem lt
'0' writemem lt '0' data_out lt
message next_state lt memory_write when
memory_write gt BR lt '1' address lt
"01" readmem lt '0' writemem lt
'1' data_out(7 downto 1) lt message(6 downto
0) data_out(0) lt message(7) next_state
ltcomplete
Access memory or I/O
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Lab3-Design (Bus Arbiter)
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Top Level Design
Bus master
memory
Clock divider
I/O buffer
Arbiter
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