Figure 10'1' A flipflop with an enable input'

1
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for Chapter 10
Figure 10.1. A flip-flop with an enable input.
2
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY regne IS GENERIC ( N INTEGER 4 )
PORT ( R IN STD_LOGIC_VECTOR(N-1 DOWNTO
0) Resetn IN STD_LOGIC E, Clock
IN STD_LOGIC Q OUT STD_LOGIC_VECTOR(N-1
DOWNTO 0) ) END regne ARCHITECTURE Behavior
OF regne IS BEGIN PROCESS ( Resetn, Clock
) BEGIN IF Resetn '0' THEN Q lt (OTHERS
gt '0') ELSIF Clock'EVENT AND Clock '1'
THEN IF E '1' THEN Q lt R END IF
END IF END PROCESS END Behavior
Figure 10.2. VHDL code for a n-bit register
with an enable input.
3
Figure 10.3. A shift register with
parallel-load and enable control
inputs.
4
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for Chapter 10
Figure 10.4. Code for a right-to-left shift
register with an enable input.
5
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for Chapter 10
Figure 10.5. Component declaration statements
for building blocks (Part a).
6
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for Chapter 10
Figure 10.5. Component declaration statements
for building blocks (Part b).
7
Sel
Data
Data
Figure 10.6. An SRAM cell.
8
Data
Data
0
1
Sel
0
Sel
1
Figure 10.7. A 2 x 2 array of SRAM cells.
9
d
d
d
Data inputs
0
n
1

n
2

Write
Sel
0
Sel
1
Sel
a
2
0
decoder
a
1
m
Address
-to-2
a
m
m
1

Sel
m
2
1

Read
q
q
q
Data outputs
0
n
1

n
2

Figure 10.8. A 2m x n SRAM block.
10
B

0

while
A
?
0
do
if
a

1
then
0
B

B

1

End if
Right-shift
A

End while
Figure 10.9. Pseudo-code for the bit counter.
11
Reset
S1
B
0

Load A
0
0
1
s
s
1
S3
S2
Done
Shift right A
1

A
0

?
B
B
1

0
0
a
0
1
Figure 10.10. ASM chart for the pseudo-code in
Figure 10.9.
12
0
Data
log
n
n
2
w
0
LB
L
L
Counter
LA
EB
E
Shift
E
EA
Clock
log
n
A
2
n
B
z
a
0
Figure 10.11. Datapath for the ASM chart in
Figure 10.10.
13
Figure 10.12. ASM chart for the bit counter
control circuit.
14
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for Chapter 10
Figure 10.13. VHDL code for the bit-counting
circuit (Part a).
15
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for Chapter 10
Figure 10.13. VHDL code for the bit-counting
circuit (Part b).
16
Figure 10.14. Simulation results for the
bit-counting circuit.
17
Binary
Decimal
Multiplicand
1
0
1
1
13
1
Multiplier
1
0
1

11

1101
13
1
0
1
1
13
0
0
0
0
143
1
0
1
1
Product
0
1
001111
(a)
Manual
method
P

0

i

0
n
1

for
to
do
b

1
if
then
i
P

P

A

end
if
A
Left-shift

end
for
(b)
Pseudo-code
Figure 10.15. An algorithm for multiplication.
18
Reset
S1
P
0

Load A
Load B
0
0
1
s
s
1
S3
S2
Shift left A
,
Shift right
B
Done
1
P
P
A


B
0

?
0
0
b
0
1
Figure 10.16. ASM chart for the multiplier.
19
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for Chapter 10
Figure 10.17. Datapath circuit for the
multiplier.
20
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for Chapter 10
Figure 10.18. ASM chart for the multiplier
control circuit.
21
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for Chapter 10
Figure 10.19. VHDL code for the multiplier
circuit (Part a).
22
Please see portrait orientation PowerPoint file
for Chapter 10
Figure 10.19. VHDL code for the multiplier
circuit (Part b).
23
Figure 10.20. Simulation results for the
multiplier circuit.
24
15
Q
00001111
9
140
A
100
01100
1001
B
9
1001
50
10
001
45
10
01
10000
5
1001
1110
1001
(a) An example using decimal numbers
R
101
(b) Using binary numbers
R

0

for
i

0
to
n
1
do

Left-shift
R
??A

?
if
R
B then
q

1

i
R

R
B


else
q

0

i
end
if
end
for
(c)
Pseudo-code
Figure 10.21. An algorithm for division.
25
Please see portrait orientation PowerPoint file
for Chapter 10
Figure 10.22. ASM chart for the divider.
26
0
DataB
n
DataA
LA
EB
Rsel
0
1
n
n
LR
L
E
L
Left-shift
Left-shift
Register
E
ER
w
EA
register
register
E
n
n
n
B
a
n
1

A
EQ
E
Left-shift
c
c
w
1
out
in
register

n
n
Clock
Q
R
Figure 10.23. Datapath circuit for the divider.
27
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for Chapter 10
Figure 10.24. ASM chart for the divider control
circuit.
28
10001100
1001
A Dividend
B (Divisor)
A /
Q
RR0
Clock cycle
R
Load A, B
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
Shift left
,
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
Shift left
Q
0

0
,
1
1
2
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Shift left
Q
0

0
,
3
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Shift left
Q
0

0
,
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0

4
Shift left
Q
0
0
,
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0

5
Subtract
Q
1
0
,
6
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
Subtract
Q
1

0
,
7
Subtract
Q
1

0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
,

8
Subtract
Q
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
0
0
0
Q Quotient
R Remainder
R ? R RR0 - B
Figure 10.25. An example of division using n
8 clock cycles.
29
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for Chapter 10
Figure 10.26. ASM chart for the enhanced
divider control circuit.
30
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for Chapter 10
Figure 10.27. Datapath circuit for the enhanced
divider.
31
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for Chapter 10
Figure 10.28. VHDL code for the divider circuit
(Part a).
32
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for Chapter 10
Figure 10.28. VHDL code for the divider circuit
(Part b).
33
Figure 10.29. Simulation results for the
divider circuit.
34
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for Chapter 10
Figure 10.30. An algorithm for finding the mean
of k numbers.
35
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for Chapter 10
Figure 10.31. Datapath circuit for the mean
operation.
36
Please see portrait orientation PowerPoint file
for Chapter 10
Figure 10.32. ASM chart for the control circuit.
37
Figure 10.33. Schematic of the mean circuit
with an SRAM block.
38
Figure 10.34. Simulation results for the mean
circuit using SRAM.
39

for
i

0
to
k
2
do
A

R

i

j

i

1
k
1
for
to
do
B

R

j
if
B
lt
A
then
R

B

i
R

A

j
A

R

i
end if

end for
end for
Figure 10.35. Pseudo-code for the sort
operation.
40
Please see portrait orientation PowerPoint file
for Chapter 10
Figure 10.36. ASM chart for the sort operation.
41
DataIn
ABmux
n
WrInit
0
1
n
RData
Rin
Rin
Rin
Rin
E
E
E
E
3
2
1
0
R
R
R
R
0
1
2
3
0
1
2
3
Imux
ABData
Bin
Ain
Rd
E
E
n
Clock
DataOut
lt
Bout
1
0
A
B
BltA
Figure 10.37. A part of the datapath circuit
for the sort operation.
42
0
2
2
LJ
LI
R
R
L
L
EJ
EI
E
E
Counter
Counter
Q
Q
C
C
i
j
Clock
2
z
k
2


i
2
1
0
Csel
z
k
1


j
Cmux
2
2
RAdd
1
0
Int
Imux
2
y
Rin
0
0
w
w
,
y
Rin
0
1
1
1
y
Rin
2
2
WrInit
y
Rin
En
3
3
Wr
2-to-4 decoder
Figure 10.38. A part of the datapath circuit
for the sort operation.
43
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for Chapter 10
Figure 10.39. ASM chart for the control circuit.
44
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for Chapter 10
Figure 10.40. VHDL code for the sort operation
(Part a).
45
Please see portrait orientation PowerPoint file
for Chapter 10
Figure 10.40. VHDL code for the sort operation
(Part b).
46
Please see portrait orientation PowerPoint file
for Chapter 10
Figure 10.40. VHDL code for the sort operation
(Part c).
47
DataIn
n
WrInit
n
Rin
Rin
Rin
Rin
E
E
E
E
3
2
1
0
Rout
Rout
Rout
Rout
3
2
1
0
n
n
n
n
Bin
Ain
E
E
n
Clock
n
n
A
B
Rd
Aout
lt
DataOut
BltA
Bout
Figure 10.42. Using tri-state buffers in the
datapath circuit.
48
Data
Q
D
Clock
Q
E
Figure 10.43. Clock enable circuit.
49
ff
ff
ff
ff
ff
ff
ff
ff
Clock
ff
ff
ff
ff
ff
ff
ff
ff
Figure 10.44. An H tree clock distribution
network.
50
t
Data
Chip package pin
Data
A
D
Q
Out
B
Clock
t
t
Clock
od
Figure 10.45. A flip-flop in an integrated
circuit.
51
Figure 10.46. Flip-flop timing in a chip.
52
Data
Data
Q
Q
D
D
(asynchronous)
(synchronous)
Clock
Q
Q
Figure 10.47. Asynchronous inputs.
53
V
DD
R
V
DD
S
Data
R
Data
R
R
V
(a) Single-pole single-throw switch
DD
(b) Single-pole double-throw switch with a basic
SR latch
Figure 10.48. Switch debouncing circuit.
54
Q

0

R

A


while
((R
B)
gt
0)
do

R

R
B

Q

Q
1

End while

Figure P10.1. Pseudo-code for integer division.
55
5 V
8
4
R
a
7
3
Clock
555
(output)
R
b
Timer
6
2
C
1
5
1
m
0.01
F
Figure P10.2. The 555 programmable timer chip.