Figure 10'1' A flipflop with an enable input

1
E
0
Q
Q
D
R
1
Clock
Q
(a) Circuit
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY rege IS PORT ( R, Resetn, E, Clock
IN STD_LOGIC Q BUFFER STD_LOGIC )
END rege ARCHITECTURE Behavior OF rege
IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF
Resetn '0' THEN Q lt '0' ELSIF
Clock'EVENT AND Clock '1' THEN IF E '1'
THEN Q lt R ELSE Q lt Q
END IF END IF END PROCESS END
Behavior
(b) VHDL code
Figure 10.1. A flip-flop with an enable input
2
LIBRARY ieee USE ieee.std_logic_1164.all --
right-to-left shift register with parallel load
and enable ENTITY shiftlne IS GENERIC ( N
INTEGER 4 ) PORT( R IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) L, E, w
IN STD_LOGIC Clock IN STD_LOGIC
Q BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO
0) ) END shiftlne ARCHITECTURE Behavior OF
shiftlne IS BEGIN PROCESS BEGIN WAIT UNTIL
Clock'EVENT AND Clock '1' IF L '1'
THEN Q lt R ELSE E 1 THEN Q(0) lt
w Genbits FOR i IN 1 TO N-1
LOOP Q(i) lt Q(i-1) END LOOP END
IF END PROCESS END Behavior
Figure 10.4. Code for a right-to-left shift
register with an enable input.
3
LIBRARY ieee USE ieee.std_logic_1164.all
PACKAGE components IS -- 2-to-1
multiplexer COMPONENT mux2to1 PORT ( w0, w1
IN STD_LOGIC s IN STD_LOGIC f
OUT STD_LOGIC ) END COMPONENT -- D
flip-flop with 2-to-1 multiplexer connected to
D COMPONENT muxdff PORT ( D0, D1, Sel, Clock
IN STD_LOGIC Q OUT STD_LOGIC )
END COMPONENT -- n-bit register with
enable COMPONENT regne GENERIC ( N INTEGER
4 ) PORT ( R IN STD_LOGIC_VECTOR(N-1
DOWNTO 0) Resetn IN STD_LOGIC E,
Clock IN STD_LOGIC Q OUT
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) END
COMPONENT -- n-bit right-to-left shift
register with parallel load and enable COMPONENT
shiftlne GENERIC ( N INTEGER 4 )
PORT ( R IN STD_LOGIC_VECTOR(N-1 DOWNTO
0) L, E, w IN STD_LOGIC Clock IN
STD_LOGIC Q BUFFER STD_LOGIC_VECTOR(N-1
DOWNTO 0) ) END COMPONENT continued in
Part b
Figure 10.5. Component declaration statements
for building blocks (Part a).
4
-- n-bit left-to-right shift register with
parallel load and enable COMPONENT shiftrne
GENERIC ( N INTEGER 4 ) PORT ( R
IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) L, E,
w IN STD_LOGIC Clock IN STD_LOGIC
Q BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO
0) ) END COMPONENT -- up-counter that
counts from 0 to modulus-1 COMPONENT upcount
GENERIC ( modulus INTEGER 8 ) PORT (
Resetn IN STD_LOGIC Clock, E, L IN
STD_LOGIC R IN INTEGER RANGE 0 TO
modulus-1 Q BUFFER INTEGER RANGE 0
TO modulus-1 ) END COMPONENT --
down-counter that counts from modulus-1 down to
0 COMPONENT downcnt GENERIC ( modulus
INTEGER 8 ) PORT ( Clock, E, L IN
STD_LOGIC Q BUFFER INTEGER RANGE 0
TO modulus-1 ) END COMPONENT END components
Figure 10.5. Component declaration statements
for building blocks (Part b).
5
LIBRARY ieee USE ieee.std_logic_1164.all
LIBRARY work USE work.components.shiftrne
ENTITY bitcount IS PORT( Clock, Resetn IN
STD_LOGIC LA, s IN STD_LOGIC
Data IN STD_LOGIC_VECTOR(7 DOWNTO 0)
B BUFFER INTEGER RANGE 0 to 8
Done OUT STD_LOGIC ) END bitcount
ARCHITECTURE Behavior OF bitcount IS TYPE
State_type IS ( S1, S2, S3 ) SIGNAL y
State_type SIGNAL A STD_LOGIC_VECTOR(7
DOWNTO 0) SIGNAL z, EA, LB, EB, low
STD_LOGIC BEGIN FSM_transitions PROCESS (
Resetn, Clock ) BEGIN IF Resetn '0'
THEN y lt S1 ELSIF (Clock'EVENT AND Clock
'1') THEN CASE y IS WHEN S1
gt IF s '0' THEN y lt S1 ELSE y lt S2
END IF WHEN S2 gt IF z '0'
THEN y lt S2 ELSE y lt S3 END IF WHEN
S3 gt IF s '1' THEN y lt S3 ELSE y lt
S1 END IF END CASE END IF END
PROCESS continued in Part b
Figure 10.13. VHDL code for the bit-counting
circuit (Part a).
6
FSM_outputs PROCESS ( y, A(0) ) BEGIN EA lt
'0' LB lt '0' EB lt '0' Done lt '0'
CASE y IS WHEN S1 gt LB lt '1' WHEN
S2 gt EA lt '1' IF A(0) '1' THEN EB
lt '1' ELSE EB lt '0' END IF WHEN S3
gt Done lt '1' END CASE END PROCESS
-- The datapath circuit is described
below upcount PROCESS ( Resetn, Clock
) BEGIN IF Resetn '0' THEN B lt 0
ELSIF (Clock'EVENT AND Clock '1')
THEN IF LB '1' THEN B lt 0 ELSEIF
EB '1' THEN B lt B 1 END IF END
IF END PROCESS low lt '0' ShiftA
shiftrne GENERIC MAP ( N gt 8 ) PORT MAP (
Data, LA, EA, low, Clock, A ) z lt '1' WHEN A
"00000000" ELSE '0' END Behavior
Figure 10.13. VHDL code for the bit-counting
circuit (Part b).
7
0
DataA
LA
DataB
LB
n
n
n
L
L
Shift-left
Shift-right
EA
EB
E
E
register
register
A
B
Clock
n
2n

z
b
Sum
0
0
2n
2n
1
0
Psel
2n
DataP
E
EP
Register
2n
P
Figure 10.17. Datapath circuit for the
multiplier.
8
Figure 10.18. ASM chart for the multiplier
control circuit.
9
LIBRARY ieee USE ieee.std_logic_1164.all USE
ieee.std_logic_unsigned.all USE
work.components.all ENTITY multiply
IS GENERIC ( N INTEGER 8 NN INTEGER
16 ) PORT ( Clock IN STD_LOGIC
Resetn IN STD_LOGIC LA, LB, s
IN STD_LOGIC DataA IN STD_LOGIC_VECTOR(N
1 DOWNTO 0) DataB IN STD_LOGIC_VECTOR(N1
DOWNTO 0) P BUFFER
STD_LOGIC_VECTOR(NN1 DOWNTO 0) Done
OUT STD_LOGIC ) END multiply ARCHITECTURE
Behavior OF multiply IS TYPE State_type IS ( S1,
S2, S3 ) SIGNAL y State_type SIGNAL
Psel, z, EA, EB, EP, Zero STD_LOGIC SIGNAL
B, N_Zeros STD_LOGIC_VECTOR(N1 DOWNTO 0)
SIGNAL A, Ain, DataP, Sum
STD_LOGIC_VECTOR(NN1 DOWNTO 0)
BEGIN FSM_transitions PROCESS ( Resetn,
Clock ) BEGIN IF Resetn '0 THEN y lt S1
ELSIF (Clock'EVENT AND Clock '1')
THEN CASE y IS WHEN S1 gt IF s '0'
THEN y lt S1 ELSE y lt S2 END IF WHEN
S2 gt IF z '0' THEN y lt S2 ELSE y lt S3
END IF WHEN S3 gt IF s '1' THEN y
lt S3 ELSE y lt S1 END IF END CASE
END IF END PROCESS continued in Part
b
Figure 10.19. VHDL code for the multiplier
circuit (Part a).
10
FSM_outputs PROCESS ( y, s, B(0) ) BEGIN EP
lt '0' EA lt '0' EB lt '0' Done lt '0'
Psel lt '0' CASE y IS WHEN S1 gt EP lt
'1 WHEN S2 gt EA lt '1' EB lt '1'
Psel lt '1 IF B(0) '1' THEN EP lt '1'
ELSE EP lt '0' END IF WHEN S3 gt Done
lt '1 END CASE END PROCESS - - Define
the datapath circuit Zero lt '0' N_Zeros lt
(OTHERS gt '0' ) Ain lt N_Zeros DataA
ShiftA shiftlne GENERIC MAP ( N gt NN
) PORT MAP ( Ain, LA, EA, Zero, Clock, A )
ShiftB shiftrne GENERIC MAP ( N gt N
) PORT MAP ( DataB, LB, EB, Zero, Clock, B )
z lt '1' WHEN B N_Zeros ELSE '0' Sum lt A
P - - Define the 2n 2-to-1 multiplexers
for DataP GenMUX FOR i IN 0 TO NN1
GENERATE Muxi mux2to1 PORT MAP ( Zero, Sum(i),
Psel, DataP(i) ) END GENERATE RegP regne
GENERIC MAP ( N gt NN ) PORT MAP ( DataP,
Resetn, EP, Clock, P ) END Behavior
Figure 10.19. VHDL code for the multiplier
circuit (Part b).
11
Reset
S1
R
0

C
n
1


,
Load A
Load B
0
1
s
0
1
S2
s
Shift left RA
S3
S4

C
C
1

Done
0
1
R
B
³
?
Shift 1 into Q
Shift 0 into Q
R
R
B


1
0
C
0

?
Figure 10.22. ASM chart for the divider.
12
Figure 10.24. ASM chart for the divider control
circuit.
13
Figure 10.26. ASM chart for the enhanced
divider control circuit.
14
DataB
LA
DataA
EB
n
n
L
E
Left-shift
Register
EA
E
w
register
Clock
n
n
B
c
c
1
out
in

n
0
n
Rsel
0
1
ER0
rr
L
LR
0
0
0
Left-shift
ER
w
E
Q
D
register
1
q
n
1

Q
n
n
n
1

r
¼
r
n
2

0
n
n
Q
R
Figure 10.27. Datapath circuit for the enhanced
divider.
15
Figure 10.28. VHDL code for the divider circuit
(Part a).
16
Figure 10.28. VHDL code for the divider circuit
(Part b).
17
Sum

0


i

k
1
for
down
to
0
do
Sum

Sum
R
i
end
for
M

Sum

k

(a)
Pseudo-code
Reset
S1
Sum
0


,
C
k
1

Load registers
0
s
1
S2
Sum
Sum
R


i

C
C
1

0
0
C
0

?
s
1
1
S4
S3


Done
M
Sum
k
(b)
ASM
chart
Figure 10.30. An algorithm for finding the mean
of k numbers.
18
Figure 10.31. Datapath circuit for the mean
operation.
19
Figure 10.32. ASM chart for the control circuit.
20
Reset
S1
0

C
i
Load registers
0
s
1
S2


,
A
R
C
C
i
j
i
S3

C
C
1

C
C
1


j
j
i
i
S4
B
R

j
S5
S6
1
C
C
1


R
A

B
A
lt
?
j
j
j
0
S7
R
B

i
S8
A
R

i
0
C
k
1


?
j
S9
1
0
Done
s
1
0
1
C
k
2


?
i
Figure 10.36. ASM chart for the sort operation.
21
Reset
S1
LI
EI
Int
0

,
,
0
s
1
S2
,
,
,
,
Int
1

Csel
0

Ain
LJ
EJ
S3
EJ
EI
S4
Bin
Csel
1

Int
1

,
,
S5
S6
1
,
,
,
EJ
Csel
1

Int
1

Wr
Aout
BltA
0
S7
Csel
0

Int
1

Wr
Bout
,
,
,
S8
Csel
0

Int
1

Ain
,
,
0
z
j
S9
1
0
Done
s
1
0
1
z
i
Figure 10.39. ASM chart for the control circuit.
22
Figure 10.40. VHDL code for the sort operation
(Part a).
23
Figure 10.40. VHDL code for the sort operation
(Part b).
24
Figure 10.40. VHDL code for the sort operation
(Part c).
25
(a) Loading the registers and starting the sort
operation
(b) Completing the sort operation and reading the
registers
Figure 10.41. Simulation results for the sort
operation.