Equivalence Checking Using Cuts and Heaps

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Equivalence Checking Using Cuts and Heaps

• Andreas Kuehlmann
• Florian Krohm
• IBM Thomas J. Watson Research Center
• Presented by Zhenghua Qi

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Previous approachesBDD

• Equivalence checking in combinational
  verification
• BDD based approaches
• The functions of the two circuits to be
  compared are converted into canonical forms which
  are then structurally compared.
• Advantages Efficient
• Disadvantages Exponential memory complexity

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Previous approachesCutpoint

• Cutpoint-based verification
• Three phases
• Choose cut-points
• The overall verification task is partitioned
  along these cutpoints into a set of smaller
  verification problems which are solved
  independently
• Eliminate false negatives

PO
PI
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Previous approachesFalse Negatives

• False Negatives
• Two functions are equivalent, but the
  verification algorithm declares them as
  different.
• Methods to handle false negatives
• Based on re-substitution
• Based on cut frontiers
• Based on ATPG (Automatic Test Pattern Generation)
  technique

• Let f1(x)g1(x) ?x
• if f2(z,y) ? g2(z,y), ?z,y then f2(f1(x),y)
  ? g2(f1(x),y) ? F ? G
• if f2(z,y) ? g2(z,y), ?z,y ?? f2(f1(x),y)
  ? g2(f1(x),y) ? F ? G

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Presented Approach

• The verification technique presented in this
  paper, utilizes BDDs, circuit graph hashing,
  cutpoint guessing and false negative elimination.
  
• Differences from previous approaches
• The processing of BDDs is prioritized by their
  size and limited to an upper bound
• The BDD construction is not stopped at cutpoints.

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Verification Overview

• Implemented as a Boolean reasoning engine.

G
F
Boolean functions
Construct circuit graph Identify equivalent parts
using hash table
Compute BDDs Identify equal functions Mark
potential cutpoints
Inject new BDDs using cutpoints
Check false negatives
Equal/Not Equal
Undecided
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Basic Algorithm for Equivalence Checking

• Basic procedure
• Construct circuit model using two-input AND gates
  and inverters.
• Perform actual comparison

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Circuit graph manipulationexample
(a) Two functionally identical circuits
(c) BDDs are computed for vertices 1, 2, 3, 4, 5
(b) Original graph for both circuits
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Circuit graph manipulationexample
(a) Two functionally identical circuits
(e) Forward hashing causes 7 and 8 to merge and
solves the verification problem
(d) BDD is computed for 6 which causes 6 and 2 to
merge
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Advanced Algorithm Using Cut Frontiers

• All vertices that have been merged are now used
  as cutpoints to inject new BDD variables onto the
  heap
• All cutpoints with identical cut levels are
  assigned to a cut frontier

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Elimination of False Negatives

• Cutpoint variables need to be resubstituted by
  their driving functions
• The elimination process is controlled by a heap
• Initialize heap with all BDDs
• Take the BDD with smallest size, re- substitute
  its topmost cut variable

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Practical Experiments

• Validate the assumptions that many industrial
  circuits are structurally similar
• The technique was measured for a number of IBM
  internal circuits

Number of functionally equivalent vertices versus
total number of vertices in typical circuit graphs
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Practical Experiments
Verification performance for selected circuits
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Conclusions

• The paper presents a new method to perform
  functional comparison of combinational circuits
  using BDDs, circuit graph hashing , cutpoint
  guessing and false negative elimination.
• The presented approach performs efficiently for a
  wide variety of designs with some degree of
  structural similarity.