Synthesis of Sequential Logic 2

1
Synthesisof Sequential Logic 2

• Lecture 23

2
State Machines

• Example 9.23
• Some style use more latches than others

3
Comparison

• Example 9.23

4
State Encoding

• Figure 9.48

5
Gated Clock

• Low power design
• Turn off activity of entire block
• Figure 9.51 (bad) and 9.52 (good)

6
Other Issues

• No mixture of posedge and negedge for the same
  signal
• Include reset

7
Pipelined Adder

• Example 9.18
• We will do a pipelined microprocessor

8
Synthesis of Nets

• Internal nets may be omitted
• Output nets are synthesized
• Example 10.1

9
Synthesis of Reg Var

• Integers are implemented as 32 bit registers
• All constants should be given a size (e.g., 4b7)
• Register sizes will be reduced
• Real, time, realtime are not synthesized
• Memory is synthesized as register arrays

10
Synthesis of X and Z

• X and Z are not synthesizable
• Use only in case, casex and casex, and treat as
  dont care