Interface Design Compute Memory Timing

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Interface DesignComputeMemory Timing

• Omid Fatemi
• (omid_at_fatemi.net)

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Outline

• Connecting to micro-processor
• Timing of microprocessor
• Timing of memory
• Interfacing memory

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Typical Interface Design
Connect
Sense Reality Touch Reality Connect Transform
Embedded Systems Micros Assembler,
C Real-Time Memory Peripherals Timers DMA
Busses Protocols Standards PCI IEEE488 SCSI USB
FireWire CAN
PC interfaces HCI
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Processor Timing Diagramfor any memory read
machine cycle
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Processor Timing Diagramfor any memory write
machine cycle
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When interfacing memory chips to a
microprocessor, consider the following

• TAVDV address access time
• TRLDV read access time
• TDVWH memory setup time
• TWHDX data hold time
• TWLWH write pulse width
• Refer to 8088 data manual

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Address Access Time (TAVDV)
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Timing Requirements during Memory Read

• TAVDV
• 3TCLCL TCLAV TDVCL
• Address Access Time
• from Address is Valid to Data is Valid

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Read Access Time (TRLDV)
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Timing Requirements during Memory Read

• TRLDV
• 2TCLCL TCLRL TDVCL
• Read Access Time
• from Read Signal is Low to Data is Valid

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Memory Setup Time (TDVWH)
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Timing Requirements during Memory Write

• TDVWH
• 2TCLCL TCLDV TCVCTX
• Memory Setup Time
• from Data is Valid to Write Signal is High

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Data Hold Time (TWHDX)
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Timing Requirements during Memory Write

• TWHDX
• TCLCH X
• Data Hold Time (after WR)
• from Write Signal is High to Data is Invalid
  (Inactive)

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Write Pulse Width / Write-Time (TWLWH)
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Timing Requirements during Memory Write

• TWLWH
• 2TCLCL Y
• Write Pulse Width / Write-Time
• from Write Signal is Low to Write Signal is High

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8088 MINIMUM COMPLEXITY SYSTEM TIMING
REQUIREMENTS
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Computation of Timing Requirements for 8088 using
a 4Mhz Clock

• TAVDV
• 3TCLCL TCLAVmax TDVCLmin
• 3(250 ns) 110 ns 30 ns
• 610 ns
• TRLDV
• 2TCLCL TCLRLmax TDVCLmin
• 3(250 ns) 165 ns 30 ns
• 555 ns

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8088 MINIMUM COMPLEXITY SYSTEM TIMING
REQUIREMENTS
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Computation of Timing Requirements for 8088 using
a 4Mhz Clock

• TDVWH
• 2TCLCL TCLDVmax TCVCTXmin
• 2(250 ns) 110 ns 10 ns
• 400 ns
• TWHDX
• TCLCH X
• 118 ns 30 ns
• 88 ns
• TWLWH
• 2TCLCL Y
• 2(250 ns) 60 ns
• 440 ns

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Timing Requirements for 8088 using a 4Mhz Clock

• TAVDV 610 ns
• TRLDV 555 ns
• TDVWH 400 ns
• TWHDX 88 ns
• TWLWH 440 ns

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Can we interface a 6264 to the 8088 chip which
uses a 4MHz clock?
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Timing Requirements for 6264 SRAM

• TAVDV ?
• TRLDV ?
• TDVWH ?
• TWHDX ?
• TWLWH ?

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HM6264B Series Read TIMING REQUIREMENTS
Chip deselection in to output in
0

30

0

35

ns

HZ2

high
-
Z (CS2)

t
Output disable to output in high
-
Z

0

30

0

35

ns

OHZ

t
Output hold from address change

10


10


ns

OH


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HM6264B Series Write TIMING REQUIREMENTS
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HM6264B Series Read Timing Diagram
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HM6264B Series Write Timing Diagram
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Timing Requirements for 6264 SRAM

• TAVDV tAA
• TRLDV tOE
• TDVWH tDW
• TWHDX tDH
• TWLWH tWP

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Timing Requirements for HM6264B-8L

• TAVDV tAA ?
• TRLDV tOE ?
• TDVWH tDW ?
• TWHDX tDH ?
• TWLWH tWP ?

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HM6264B Series Read TIMING REQUIREMENTS
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HM6264B Series Write TIMING REQUIREMENTS
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Timing Requirements for HM6264B-8L

• TAVDV tAA 85 ns
• TRLDV tOE 45 ns
• TDVWH tDW 40 ns
• TWHDX tDH 0 ns
• TWLWH tWP 55 ns

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Comparing Timing Requirements of 8088 (using 4
Mhz clock) and HM6264B-8L
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Can we interface a 2764 to the 8088 chip which
uses a 4MHz clock?
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Timing Requirements for 2764 EPROM

• TAVDV ?
• TRLDV ?
• TDVWH ?
• TWHDX ?
• TWLWH ?

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M2764A Read Mode AC Characteristics
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M2764A Read Mode Timing Diagram
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Timing Requirements for 2764 EPROM

• TAVDV tAVQV
• TRLDV tGLQV
• TDVWH N/A
• TWHDX N/A
• TWLWH N/A

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Timing Requirements for 2764 EPROM

• TAVDV tAVQV ?
• TRLDV tGLQV ?
• TDVWH N/A
• TWHDX N/A
• TWLWH N/A

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M2764A Read Mode AC Characteristics
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Timing Requirements for M2764A-3

• TAVDV tAVQV 180 ns
• TRLDV tGLQV 65 ns
• TDVWH N/A
• TWHDX N/A
• TWLWH N/A

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Comparing Timing Requirements of 8088 (using 4
Mhz clock) and M2764A-3
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What if we need to interface a slow memory to
the 8088?
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Comparing Timing Requirements of 8088 (using 4
Mhz clock) and a certain slow memory chip
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RecallWrite Pulse Width / Write-Time (TWLWH)
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Write Pulse Width / Write-Time (TWLWH) w/ 1 wait
state
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Comparing Timing Requirements of 8088 (using 4
Mhz clock) and a certain memory chip
caused by 1 wait state during a memory write on
the slow memory chip
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How do we produce a wait state?

• By turning the READY input of the 8088
  microprocessor to LOW

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Requirements for the READY input of the 8088
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Requirements for the RDY of the 8284
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