FEDv1 Final Firmware Subtasks

1
FEDv1 Final Firmware Subtasks
15th May 2003
System ACE
EPROM
VME FPGA
Ed
DAC
EPROM
Opto Rx
Temp
System ACE
ADC
DAC
VME Bus
Opto Rx
Temp
VME
ADC
Temp
I2C
Clocks
Serial Comms
Regs
Clocks
Serial Comms
Regs
Serial Comms
VME LINK
Input
Data
Data
Header Mode
Header Mode
Cluster Mode
Input
Ed
FIFOs
Scope Mode
Output
DELAY FPGA x 3 x 8
BE FPGA
Saeed
Scope Mode
Serial Comms
VME Link
Regs
External Devices
FE FPGA x 8
Ivan
To be Implemented
S-LINK
S-LINK
Control
Clocks
Headers
Under Simulation
Throttle
TCS
Input
Under Test on FED
QDR Write
QDR Read
TTC chanA
TTCrx
Data Readout
Saeed, Ivan
Working on FED
Chan B
QDRs
Controls
Ed, John
FEDv2
2
FEDv1 Final Firmware Subtasks
11th June 2003
System ACE
EPROM
VME FPGA
Ed
DAC
EPROM
Opto Rx
Temp
System ACE
ADC
DAC
VME Bus
Opto Rx
Temp
VME
ADC
Temp
I2C
Clocks
Serial Comms
Regs
Clocks
Serial Comms
Regs
Serial Comms
VME LINK
Input
Data
Data
Header Mode
Header Mode
Cluster Mode
Input
Ed
FIFOs
Scope Mode
Output
DELAY FPGA x 3 x 8
BE FPGA
Saeed
Scope Mode
Serial Comms
VME Link
Regs
External Devices
FE FPGA x 8
Ivan
To be Implemented
S-LINK
S-LINK
Control
Clocks
Headers
Under Simulation
Throttle
TCS
Input
Under Test on FED
QDR Write
QDR Read
TTC chanA
TTCrx
Data Readout
Saeed, Ivan
Working on FED
Chan B
QDRs
Controls
Ed, John
FEDv2
3
FEDv1 Final Firmware Subtasks
26th June 2003
System ACE
EPROM
VME FPGA
Ed
DAC
EPROM
Opto Rx
Temp
System ACE
ADC
DAC
VME Bus
Opto Rx
Temp
VME
ADC
Temp
I2C
Clocks
Serial Comms
Regs
Clocks
Serial Comms
Regs
Serial Comms
VME LINK
Input
Data
Data
Header Mode
Header Mode
Cluster Mode
Input
Ed
FIFOs
Scope Mode
Output
DELAY FPGA x 3 x 8
BE FPGA
Saeed
Scope Mode
Serial Comms
VME Link
Regs
External Devices
FE FPGA x 8
Ivan
To be Implemented
S-LINK
S-LINK
Control
Clocks
Headers
Under Simulation
Throttle
TCS
Input
Under Test on FED
QDR Write
QDR Read
TTC chanA
TTCrx
Data Readout
Saeed, Ivan
Working on FED
Chan B
QDRs
Controls
Ed, John
FEDv2
4
FEDv1 Final Firmware Subtasks
23rd July 2003
System ACE
EPROM
VME FPGA
Ed
DAC
EPROM
Opto Rx
Temp
System ACE
ADC
DAC
VME Bus
Opto Rx
Temp
VME
ADC
Temp
I2C
Clocks
Serial Comms
Regs
Clocks
Serial Comms
Regs
Serial Comms
VME LINK
Input
Data
Data
Header Mode
Header Mode
Cluster Mode
Input
Ed
FIFOs
Scope Mode
Output
DELAY FPGA x 3 x 8
BE FPGA
Saeed
Scope Mode
Serial Comms
VME Link
Regs
External Devices
FE FPGA x 8
Ivan
To be Implemented
S-LINK
S-LINK
Control
Clocks
Headers
Under Simulation
Throttle
TCS
Input
Under Test on FED
QDR Write
QDR Read
TTC chanA
TTCrx
Data Readout
Saeed, Ivan
Working on FED
Chan B
QDRs
Controls
Ed, John
FEDv2
5
FEDv1 Final Firmware Subtasks
22nd August 2003
System ACE
EPROM
VME FPGA
Ed
DAC
EPROM
Opto Rx
Temp
System ACE
ADC
DAC
VME Bus
Opto Rx
Temp
VME
ADC
Temp
I2C
Clocks
Serial Comms
Regs
Clocks
Serial Comms
Regs
Serial Comms
VME LINK
Input
Data
Data
Header Mode
Header Mode
Cluster Mode
Input
Ed
FIFOs
Scope Mode
Output
DELAY FPGA x 3 x 8
BE FPGA
Saeed
Scope Mode
Serial Comms
VME Link
Regs
External Devices
FE FPGA x 8
Ivan
To be Implemented
S-LINK
S-LINK
Control
Clocks
Headers
Under Simulation
Throttle
TCS
Input
Under Test on FED
QDR Write
QDR Read
TTC chanA
TTCrx
Data Readout
Saeed, Ivan
Working on FED
Chan B
QDRs
Controls
Ed, John
FEDv2
6
FEDv1 Final Firmware Subtasks
4th November 2003
System ACE
EPROM
VME FPGA
Ed-gtSaeed
DAC
EPROM
Opto Rx
Temp
System ACE
ADC
DAC
VME Bus
Opto Rx
Temp
VME
ADC
Clocks
I2C
Clocks
Serial Comms
Regs
Clocks
Serial Comms
Regs
Data
Serial Comms
VME LINK
Input
Spy
Data
Header Mode
Header Mode
Cluster Mode
Input
Ed-gtSaeed
FIFOs
Scope Mode
Output
DELAY FPGA x 3 x 8
BE FPGA
Saeed
Scope Mode
Serial Comms
VME Link
Regs
External Devices
FE FPGA x 8
Saeed
To be Implemented
S-LINK
S-LINK
Control
Headers
Under Simulation
Throttle
TCS
Input
Under Test on FED
QDR Write
QDR Read
TTC chanA
TTCrx
Data Readout
Saeed, Ivan
Working on FED
Chan B
QDRs
Controls
Ed, John
FEDv2