My%20Little%20Computer%20%20%20Jon%20Andrews%20Supervisor:%20J%20Garside

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My Little Computer
Jon AndrewsSupervisor J Garside
Project OutlineTo implement a real commercial
processor into an Field Programmable Gate Array
(FPGA). It should be able to run code from the
original processor. Processor 8080, 6800, 6502,
PDP-8 Digital Equipment Corporation PDP-8 12 Bit
CISC Machine4K Words of Memory8 Basic
InstructionsOperating System DEC
OS/8 History 100,000 Machines SoldPDP-8/I
Introduced in 1968Last Machine Built In 1984
(PDP-8/A)
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Instruction Set

• Instructions
• AND, TAD, ISZ, DCA, JMP, JMS, IOT, OP
• Instruction Set Format
• 3 Bits for Opcode 7 Bits for address
• 12-bit Memory Location is Inferred
• Key Features
• Jump to Sub Routine
• Return Address Stored in 0
• Auto Indexing
• Instruction Set Flow Control (no conditional
  branch)
• 13 Microcoded Instructions

Page Layout
12 Bits
Page 0
Page 1
Page 32
Page 31
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Example Instruction

• E.G. 001 11 11000012 AT Location 17438
• Instruction Twos Complement ADDIndirect
  Bit 1Page Bit 1Page Offset 1100001EA
  (17418) 10018CA (10018) 52128
• This will give AC lt- AC 52128

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Processor Operation

• Original PDP-8
• 7 Fetch States
• 6 Executions States
• 1 IDLE State
• Total 14 States
• My Implementation
• 5 Generic States
• Reasons For Reduction
• Larger Transistor Budget
• Ability to Operations in Parallel
• Faster Memory
• More Buses

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State Diagram
IDLE
F0
Instructions Fetched
Execution Complete
Microcode Incomplete
F1
E0
Get Operand (Direct)
Auto Index Written to Memory (deferred) Get
Operand
Get Operand (InDirect)
Get Operand Addr (InDirect)
F2
E1
Auto Index Calculation

• F0
• Start State
• Loop in this state when IDLE
• F1
• Address of Operand Calculated
• F2
• Address Read from operand to fetch indirected
  data
• E0
• Instruction execution, eg ADD
• Loop in this state when microcoded instruction
  being processed
• E1
• Updates the Auto Index value of memory

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Conclusion

• Change in design due to technology
• Move towards RISC
• Single Cycle Execution
• Register-Register, not Memory
• More Functionality now introduced
• Sub, Multiply
• Increased performance
• Cycle time can be reduced due to the speed of
  electronics
• Execution states dramatically reduced

Time Scale

• Data Path Mid Nov
• ALU functional blocks End Nov
• Control End Dec
• Test Programs End Feb
• Time Permitting
• I/O Interface
• Focal

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Data Path