A Cocktail Approach on Random Access Scan toward Low Power and High Efficiency Test

1
A Cocktail Approach on Random Access Scan toward
Low Power and High Efficiency Test

• Shih Ping Lin and Chung Len Lee
• Dept. of Electronics Engineering, National Chiao
  Tung University, Hsin Chu, Taiwan

Jwu E Chen Dept. of Electrical Engineering,
National Central University, Chung Li, Taiwan
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Scan Test

• Widely used for todays designs
• Large amount of test data for state-of-art
  designs
• Large amount of switching activity during pattern
  scanning

To reduce test volume, power and time
3
Architecture and Scan Cell of Random Access Scan
(RAS)
CUT

SFFs
Scan Enable
Decoder
Address Shift Register
Si

RAS Architecture
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The Flow for Pattern Preparation
Second Phase
First Phase
Test Vector Reordering
Our ATPG for Test Cubes Generation
Cycle Random Scan Test
Constrained Static Compression
Bit-Propagation Vector Dropping
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Cycle Random Scan Test s5378
test length 16
4 random pattern seeds fault coverage 72
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The Proposed ATPG

• Considers the percentage of unspecified bits
  during the test compaction step of test
  generation (according to a threshold).
• Produces a reasonable number of test cubes with
  high percentage of dont care bits.
• Increases the flexibility of test vector
  reordering.

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Test Vector Reordering

• Test vector reordering is an important technique
  to solve the Minimum Bit Flips Problem (MBFP).
• Given two test cubes, v1 and v2, the cost of v1
  changing to v2 is defined as
• Optimality of reordering may be lost due to the
  use of different cost models.

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Cost Models for Test Vector Reordering
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Constraint Static Compaction

• Traditional Static Compaction
• compacts test cubes as much as possible
• increases the number of bit flips greatly
• Constrained Static Compaction (CSC)
• compacts a cube only with those compatible cubes
  following it.
• keeps the number of bit flips unchanged

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CSC An Example
0x11, x111 1x1x, x1xx, 1xx0
0x11 1x1x x1xx x111 1xx0
0x11 111x x111 1xx0
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Bit-Propagation before Test Vector Dropping
(BPBTVD) Strategy

• After CSC, pad dont care bits of test cubes by
  its prior test cubes.

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Padding Xs
test cubes 0x11 1x00 010x x111 1xx0
vectors 0011 1000 0100 0111 1110
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Bit-Propagation before Test Vector Dropping
(BPBTVD) Strategy

• After CSC, pad dont care bits of test cubes by
  its prior test cubes.
• Fault simulate to find out test cubes that do not
  detect any fault.

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Fault Simulation
faults detected 5 0 1 2 3
test cubes 0x11 1x00 010x x111 1xx0
vectors 0011 1000 0100 0111 1110
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Bit-Propagation before Test Vector Dropping
(BPBTVD) Strategy

• After CSC, pad dont care bits of test cubes by
  its prior test cubes.
• Fault simulate to drop test cubes that do not
  detect any fault.
• Propagate important bits of the dropped test cube
  to its followed test cube
• maintains the same fault coverage.

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Without BPBTVD An Example
test cubes 0x11 1x00 010x x111 1xx0
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BPBTVD An Example
test cubes 0x11 1x00 010x x111 1xx0
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Experimental Result of The Proposed Process to
Solve MBFP
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Volume and Time Reduction Obtained by Cocktail
Approach
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Power Reduction Obtained for RAS Scheme
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Conclusion

• The proposed scheme adopts
• Cycle Random Scan Test
• A Proposed ATPG
• Test Vector Reordering
• Constraint Static Compaction
• Bit-Propagation Before Test Vector Dropping
• The proposed scheme saves
• Test data volume, time and power

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Q A
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Modified Address Register
Mode
Si
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Serial Scan Mode - Counter
1
Si
25
Random Access Scan Mode Shift Register
0
Si
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Impact of Adopting RAS

• Scan cells
• Area
• Scan In/Out and Scan Enable
• Routing Area
• Signal Integrity

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Gate Overhead of Scan Cells

• As technique advances, a chip can has more gates.

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Area Overhead
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Routing of Scan Enable (1/2)

• Routing area can be reduced by using hierarchical
  decoders and by carefully laying out.

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Routing of Scan Enable (2/2)

• Address shift registers are triggered at negative
  clock edge to avoid the delay effect of scan
  enable.
• Buffer insertion can also be used if signal
  integrity does not meet.

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Output Compactor

• If an MISR is used, the area and test power will
  increase greatly.
• Combinational compactor can be utilized, such as
  an X-Compactor ITC02

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Static Compaction

• Two test cubes are compatible if they do not have
  conflict bits (1/0) at any position.
• Ex

0x110x
0x110x
xx1xx1
1x1xx1