the Operating System (OS)

1
the Operating System (OS)
2
The Operating System (OS)
Operating System
P1 Editor
P2 Compiler
P3 Quake Arena
MIPS
At any one time the processor (MIPS) is only
excecuting one program (process).
3
The Operating System (OS)
Operating System
P1 Editor
P2 Compiler
P3 Quake Arena
MIPS
At any one time the processor (MIPS) is only
excecuting one program (process).
4
The Operating System (OS)
Operating System
P1 Editor
P2 Compiler
P3 Quake Arena
MIPS
At any one time the processor (MIPS) is only
excecuting one program (process).
5
The Operating System (OS)
Operating System
P1 Editor
P2 Compiler
P3 Quake Arena
MIPS
At any one time the processor (MIPS) is only
excecuting one program (process).
6
The Operating System (OS)
Operating System
P1 Editor
P2 Compiler
P3 Quake Arena
MIPS
At any one time the processor (MIPS) is only
excecuting one program (process).
7
Our Assembler
.text
.data
User
.kdata
.ktext
Kernel
8
The Hardware
.text
.data
User
ERROR!
OK
.kdata
.ktext
Kernel
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How does the User program pass control to the
Operating System?

• Take control on ERROR
• Pass control explicitly

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ERROR

• Ex, Arithmetical Overflow
• li 4 0x80000000
• neg 4 4
• (sub 4 0 4)
• 0x00000000
• - 0x80000000
• 0x80000000

Sign differs
Same Sign ! ERROR
11
Signed/Unsigned Arithmetics

• The only difference is that
• Unsigned never causes ERROR
• Signed causes ERROR on Overflow etc.

Signed ADD SUB ADDI ..
Unsigned ADDU SUBU ADDIU ..
12
Memory Error

• Instruction Memory Bad PC
• Data Alignment Error
• Access Protected Memory from User mode
• Nonexistent Memory
• (Page fault Chapter 7)

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Do not confuse !

• A Memory that tells the pipeline to Wait
• relate to cache miss
• A Memory Error or Page Fault
• relate to TLB miss

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The Consequence

• A Memory that tells the pipeline to Wait
• Pipeline Stall
• A Memory Error or Page Fault
• Exception

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Pass Control Explicitly

• The User wants some service from the Operating
  System
• File I/O
• Graphics
• Sound
• Allocate Memory
• Terminate Program (no HALT instruction in real
  MIPS)
• SYSCALL (causes an exception)

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How to choose service

• Is there different SYSCALLs?
• NO! Only one, use a register (a0) to choose
• Use other registers (a1,...) as parameters
• Use v0 for result
• ori a1 r0 A Char A
• ori a0 r0 0x00 Write Char
• syscall
• ori a0 r0 0x01 Read Char
• syscall
• or a1 r0 v0 Move result v0-gta1
• ori a0 r0 0x00 Echo Char
• syscall

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Other ways for the Operating System to take
control?

• External Interrupts, (not caused by User program)
• Timers
• Harddisk
• Graphics
• Sound
• Keyboard, Mouse, other perhipals

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Coprocessor CP0

• 8 Bad Memory Address
• 12 Status Register
• 13 Cause Register
• 14 Exception Address (EPC)

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Status Register CP0 (12)

• Mode Stack
• External Interrupt enable/disable

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Mode Stack
OLD
PREVIOUS
CURRENT
0
5
KU IE
KU IE
KU IE
0 Kernel Mode 1 User Mode 0 External Interrupt
Disable 1 External Interrupt Enable
KU IE
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Exception / Interrupt Occurs
OLD
PREVIOUS
CURRENT
KU IE
KU IE
KU IE
KU IE
KU IE
0 0
0 Kernel Mode 1 User Mode 0 External Interrupt
Disable 1 External Interrupt Enable
KU IE
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RFE Instruction (priviliged)
OLD
PREVIOUS
CURRENT
KU IE
KU IE
KU IE
? ?
KU IE
KU IE
We restore the PREVIOUS (KU,IE) into CURRENT
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External Interrupts

• Bit 0, (Current Interrupt Enable)
• All External Interrupts Enable/ Disable
• Bit 15..10, (individual interrupt enable)

15
10
0
Current IE
INT 4
INT 3
INT 2
INT 1
INT 0
INT 5
............
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Enable External Interrupt 2

• Bit 0 1, (External Interrupt Enabled)
• Bit 12 1, Interrupt 2 Enabled

15
10
0
INT 4
INT 3
INT 2
INT 1
INT 0
INT 5
Current IE 1
............
0
0
0
0
0
1
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Cause Register (CP0 13)

• Bit 5..2, Exception Cause Code
• Bit 15..10, Interrupt Pending
• Bit 31, Exception Occur In Branch Slot

10
5
2
31
15
INT 5
INT 4
INT 3
INT 2
INT 1
Ex 3
Ex 2
Ex 1
Ex 0
BS
INT 0
....
....
...
Pending Interrupts
Exception Cause Code see LSI Logic Users Manual
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Check if Interrupt 2 Pending

• Mask with bit 12

15
10
CP0 13
INT 4
INT 3
INT 2
INT 1
INT 0
INT 5
AND
0
0
0
0
0
1
0
0
0
0
0
INT 2
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Resume User Program

• CP0 14 Holds the Exception Address
• (Addr to instruction in EX
  stage)
• mfc0 k0 14 resume address
• jr k0 k0 kernel reg
• rfe delayed branch

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Shared Stack

• Assume that the User program uses the stack
• Can the Kernel use the same stack (sp)?
• Yes, but remember never to use memory below sp,
  it will be destroyed (overwritten)!!

sp
Kernel Data
Kernel Data
sp
User Data
User Data
User Data
User Data