ECE 545 Project 2 Specification Part II

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ECE 545 Project 2Specification Part II
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Tips Hints (1)
Each entity and each package should be placed in
a different file. The name of each file should
be exactly the same as the name of an entity or
package it contains. Arrange entity names in the
bottom-up order (the top-most entity at the end
of the list) and define this list in your script
using the command blocks entity1, entity2,
, entityN

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Tips Hints (2)
Use only one clock in your entire design. Use an
identical name for the clock signal in all
your entities and packages (including
declarations of components). Use the same clock
name in all clock-related commands of your
script, such as create_clock,
set_clock_transition, etc.

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Tips Hints (3)

• Avoid advanced features, such as
• multiple clocks,
• gated clocks,
• multicycle paths,
• circular feedback loops containing only
• combinational logic.

Although these features are supported by
Synopsys, their correct use requires additional
knowledge and experience that are beyond the
scope of ECE 545.
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Tips Hints (4)
Create a project directory in your main user
directory. Create the following subdirectories
in the project directory db, docs, log,
reports, scripts, tb, vhdl. Place all your
synthesizable source files in the vhdl
directory, and your testbench files in the
tb directory. Place your scripts in the script
directory. Define at least the following
directories close to the beginning of your
script src_directory, report_directory,
db_directory.

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Tips Hints (5)
Do not change values of the constraint
conditions specified using the following script
commands set_max_fanout 100 block set_clock_late
ncy 0.1 find(clock, "clock") set_clock_transition
0.01 find(clock, "clock") set_clock_uncertainty
-setup 0.1 find(clock, "clock") set_clock_uncertai
nty -hold 0.1 find(clock, "clock") set_load 0
all_outputs() set_input_delay 1.0 -clock clock
-max all_inputs() set_output_delay -max 1.0
-clock clock all_outputs() set_wire_load_model
-library tcb013ghptc -name "TSMC8K_Fsg_Conservativ
e" You can change a clock name within these
commands if necessary. These constraints are
required to be the same for all students.

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Tips Hints (6)
Change your current directory to your log
directory before you execute design_analyzer. Aft
er executing your script within
design_analyzer, analyze the contents of log
files generated in the directory log. These
files contain the exact description of
warnings and errors generated during
synthesis. Please do your best to eliminate all
errors and majority of warnings generated by the
scripts and written to the log files.

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Project DeliverablesTask 1
Source codes of all synthesizable files you have
developed in order to meet the project
specification. Description of any changes you
have had to make in these codes in order to a.
get your codes synthesized using Synopsys with
TSMC libraries, b. eliminate all synthesis
errors and minimize the number of synthesis
warnings.
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Project DeliverablesTask 2
Source code of the comprehensive testbench
capable of verifying the operation of your
entire circuit. Input files containing test
vectors, and output files containing reports from
simulation. Short description of the procedure
you have used to generate test vectors.
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Project DeliverablesTask 3
Analysis of differences among netlists obtained
using Synopsys and Synplify Pro. The detailed
descriptions of all differences (if any) between
source codes synthesizable using Synplify Pro and
Synopsys.
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Project delivarables Task 4

• The detailed timing and area results obtained for
• all synthesized circuits, including
• maximum clock frequency
• critical path
• maximum encryption/decryption throughput
• area
• ratio maximum encryption/decryption throughput
• divided by area.

The detailed discussion of the obtained
results, containing the best possible explanation
of differences among results obtained for all
analyzed cases.