ECE 545 Project 1 Specification Part II

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ECE 545 Project 1Specification Part II
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Phase 2, due Thursday October 21, noon

• Draw a state diagram of the control unit that
  governs the
• operation of the encryption/decryption unit
  and the
• input/output interface.
• Describe the designed control unit using
  synthesizable VHDL code.
• 3. Write a testbench capable of verifying
  function of
• your control unit.
• 4. Write a testbench capable of verifying
  operation of
• the entire circuit composed of the
• encryption/decryption unit,
• control unit, and
• input/output interface.
• This testbench should read test vectors from
  a file.

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• 5. Synthesize and implement your circuit for
• RC5 32/12/16 using the smallest device of
  the
• Xilinx Spartan 2 family capable of holding
  the
• entire circuit.
• 6. For the entire implemented circuit, determine
• maximum clock frequency
• maximum encryption/decryption throughput
• area in number of CLB slices
• ratio maximum encryption/decryption throughput
  divided by area.
• 7. Verify the correct operation of your circuit
  using
• timing simulation at the frequency closed to
  the
• maximum clock frequency.

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RC5 w/r/b
w - word size in bits
w 16, 32, 64
input/output block size, m 2 words 2?w bits
Typical values w32 ? 64-bit
input/output block w64 ?
128-bit input/output block
b - key size in bytes
0 ? b ? 255
key size in bits, k 8?b bits
r - number of rounds
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Implementation of a secret-key cipher Round keys
precomputed
input control
key
input
input interface
control unit
key scheduling
encryption/decryption unit
memory of round keys
output interface
output
output control
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clock
Encryption/decryption unit with control i/o
interface
reset
encrypt/decrypt
data output
m
m
data input
write
data available
full
data read
round number
round key(s)
Key memory
round key(s)
cycle number
k
key input
Key scheduling unit
key available
key read
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Basic iterative architecture
multiplexer
register
combinational logic
round key
one round
Encrypt/Decrypt
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Typical Flow Diagram of a Secret-Key Block Cipher
Round Key0
optional
Initial transformation
i1
Round Keyi
Cipher Round
ii1
r times
i lt r
Round Keyrounds1
Final transformation
optional