A Worked MRTPN Example

1
A Worked MRTPN Example

• (or The Pholly of Physicists)
• (June 2005)

2
The Problem

• Brand new sensor measures inspirons.
• But, the PC-card only has one register!
• If we miss 3 readings in a row the results will
  be useless! ?
• Samples are timed, so double-reading is ok.

3
The Solution

• Model the system with outer bounds values.
• Check for triple miss.
• Three components
• sensor
• singleregister
• softwaremonitor

monitor
register
read
sensor
write
4
Sensor
off

• Takes a few moments to warm up if its cold.
• Takes a few moments to take a measurement.
• Then transfers the reading to the PC card

activate
1,3
ready
write
sample
2,4
0,1
analysing
5
Register
off

• Very simple, powers up quickly.
• Very rapid read writes.

activate
1
ready
0,1
read
write
0,1
6
Monitor
off

• Software to accumulate the results in a file.
• Reading and writing take a few moments for the
  O/S calls to execute.

activate
2,4
ready
1,2
store
read
2,3
buffering
7
Modular Algorithm

• Initial state (s0?, 0)A?
• For each state M
• find the locally reachable states, M
• lreach(M, d) (M, ?) lt (future state,
  leftover delay)
• find global events that can then be fired, tf
• (M ? M) ? (M ?, tf gt M) gt M is a new
  state!
• continue until time is exhausted for M
• lather, rinse, repeat!

8
Lets go

• Initial state(s0,0),(r0,0),(m0,0)
• Need to calculate the lreach sets for those
• For convenience
• local pairs (s,d)
• global pairs s,d
• omega pair s,d

(s0,0),(r0,0), (m0,0)
???
???
???
9
lreach(s0)
s0
0,act
off_at_0
0,act

• 0 gt (s0,0), (s1,0), (s2,0), (s3,0)
• 1 gt (s1,1), (s2,1), (s3,1), (s4,0),
• (s5,0), (s6,0)
• 2 gt (s2,2), (s3,2), (s4,1), (s5,1),
• (s6,1), (s4,0), (s5,0), (s6,0)
• 3 gt (s3,3), s4,2, (s5,2), (s6,2),
• (s4,1), (s5,1), (s6,1), (s4,0),
• (s5,0), (s4,0)
• 4gt s4,3, s5,3, (s6,3), s4,2,
• (s5,2), (s6,2), (s4,1), (s5,1),
• (s6,1)

0,act
s1
s2
s3
ready_at_-1
ready_at_-2
ready_at_-3
3
1
1
2
2
3
sample
2
1
3
s4
s6
analyse_at_-2
analyse_at_-4
s5
analyse_at_-3
2,write
3,write
4,write
5,write
3,write
4,write
10
lreach(s0) contd
s0
0,act
off_at_0
0,act

• 4gt s4,3, s5,3, (s6,3), s4,2,
• (s5,2), (s6,2), (s4,1), (s5,1),
• (s6,1)
• 5 gt s4,3, s5,4, s6,4,s5,3,
• (s6,3), s4,2, (s5,2), (s6,2)
• 6 gt s4,3, s5,4, s6,5,
• s6,4, s5,3, (s6,3)
• 7 gt s4,3, s5,4, s6,5,
• s6,4
• 8 gt s4,3, s5,4, s6,5
• Saturated! Hence O(s0) 8

0,act
s1
s2
s3
ready_at_-1
ready_at_-2
ready_at_-3
3
1
1
2
2
3
sample
2
1
3
s4
s6
analyse_at_-2
analyse_at_-4
s5
analyse_at_-3
2,write
3,write
4,write
5,write
3,write
4,write
11
lreach(m0)
m0
0,act
off_at_0
0,act

• 0 gt (m0,0), (m1,0), (m2,0), (m3,0)
• 1 gt (m1,1), (m2,1), (m3,1)
• 2 gt (m1,2), (m2,2), (m3,2)
• 3 gt m1,3, (m2,3), (m3,3)
• 4 gt m1,4, m2,4, (m3,4)
• 5 gt m1,4, m2,5, m3,5
• 6 gt m1,4, m2,5, m3,6
• Saturated! Hence O(m0) 6

0,act
m1
m3
ready_at_-2
ready_at_-4
m2
ready_at_-3
3,read
4,read
5,read
6,read
4,read
5,read
12
lreach(r0)
r0
off_at_0

• 0 gt (r0,0), (r1,0)
• 1 gt r1,1
• 2 gt r1,2
• Saturated! Hence O(r0) 2

0,act
r1
ready_at_-1
2,read
1,write
1,read
2,write
13
Back to the big picture
sg5
sg1

• Next set of states found by taking pair-wise
  matches from the modules lreach sets.
• Notice there is no (7,write) or (8,write)?
• (6, read) is a globally certain event
• stragglers will have to wait for the next state

(s7,0),(r2,0), (m0,3)
(s0,3),(r2,0), (m4,0)
3,write
3,read
sg6
sg0
sg2
(s7,0),(r2,0), (m0,4)
4,write
(s0,0),(r0,0), (m0,0)
(s0,4),(r2,0), (m4,0)
4,read
5,write
sg3
5,read
(s7,0),(r2,0), (m0,5)
(s0,5),(r2,0), (m4,0)
6,write
6,read
sg8
sg4
sg7
(s7,0),(r2,0), (m0,6)
(s0,6),(r2,0), (m4,0)
14
New States s7

• New state found.
• lreach(s7)
• 0 gt (s7,0), (s4,0), (s5,0), (s6,0)
• 1 gt (s4,1), (s5,1), (s6,1)
• 2 gt s4,2, (s5,2), (s6,2)
• 3 gt s4,3, s5,3, (s6,3)
• 4 gt s4,3, s5,4, s6,4
• 5 gt s4,3, s5,4, s6,5
• Saturated! Hence O(s7) 5

s5
analyse_at_-3
3,write
4,write
0,sample
s7
0,sample
0,sample
ready_at_0
5,write
2,write
4,write
3,write
s6
s4
analyse_at_-4
analyse_at_-2
15
New States m4
m2
ready_at_-3

• New state found.
• lreach(m4)
• 0 gt (m4,0)
• 1 gt (m4,1)
• 2 gt (m4,2), (m5,0)
• 3 gt (m4,3), m5,1, (m5,0)
• 4 gt m5,2, m5,1
• 5 gt m5,2
• Saturated! Hence O(m4) 5

m1
4,read
5,read
ready_at_-2
m3
ready_at_-4
4,read
5,read
3,read
m4
6,read
buffering_at_0
3,store
2,store
m5
ready_at_0
2,read
1,read
16
New States r2
r1

• New state found.
• lreach(r2)
• 0 gt r2,0
• 1 gt r2,1
• Saturated! Hence O(r2) 1

ready_at_-1
1,read
1,write
2,write
2,read
r2
ready_at_0
1,read
0,write
0,read
1,write
17
Back to the big picture contd
sg11
sg4

• The local state spaces are all saturated, so now
  we just need to keep exploring

(s7,0),(r2,0), (m4,0)
(s0,6),(r2,0), (m4,0)
0,write
3,read
sg12
sg1
sg9
(s7,0),(r2,0), (m4,1)
1,write
(s0,3),(r2,0), (m4,0)
(s0,7),(r2,0), (m4,0)
4,read
2,write
sg10
5,read
(s7,0),(r2,0), (m4,2)
(s0,8),(r2,0), (m4,0)
3,write
sg14
sg13
4,write
(s7,0),(r2,0), (m4,3)
5,write
sg16
sg15
(s7,0),(r2,0), (m4,5)
(s7,0),(r2,0), (m4,4)
18
Back to the big picture contd
sg7
sg11

• The exploration continues

(s7,0),(r2,0), (m0,5)
(s7,0),(r2,0), (m4,0)
2,write
0,read
sg8
sg5
sg17
(s7,0),(r2,0), (m0,6)
3,write
(s7,0),(r2,0), (m0,3)
(s7,1),(r2,0), (m4,0)
1,read
sg18
2,read
3,read
(s7,2),(r2,0), (m4,0)
sg19
(s7,3),(r2,0), (m4,0)
19
Back to the big picture contd
sg13
sg19

• And a bit more

(s7,0),(r2,0), (m4,2)
(s7,3),(r2,0), (m4,0)
2,write
3,read
sg14
sg11
sg20
(s7,0),(r2,0), (m4,3)
3,write
(s7,0),(r2,0), (m4,0)
(s7,4),(r2,0), (m4,0)
4,read
4,write
5,read
(s7,0),(r2,0), (m4,4)
(s7,5),(r2,0), (m4,0)
5,write
sg16
sg15
(s7,0),(r2,0), (m4,5)
sg21
20
Back to the big picture contd
sg11
sg21

• And some congruent activity

(s7,0),(r2,0), (m4,0)
(s7,5),(r2,0), (m4,0)
0,write
3,read
sg12
sg18
(s7,0),(r2,0), (m4,1)
1,write
(s7,2),(r2,0), (m4,0)
2,write
(s7,0),(r2,0), (m4,2)
3,write
sg14
sg13
(s7,0),(r2,0), (m4,3)
21
O Limits

• We will only find events in these ranges
• write ? (s0, 3,8) U (s7, 2,5)
• read ? (m0, 3,6) U (m4, 3,5)
• both of these dominate the register ranges.
• In practise a real tool would probably throw
  out most of the lreach data once the event ranges
  for each entry state have been calculated.

22
Guestimating SG

• From the previous ranges we know that s7 and m4
  can only go up to 5s before they will definitely
  go off.
• so there are less than 12 core states because
  at least two modules will always be 0
• plus we need to clear the initialisation delays
  out at the start, less than 14 states
• Should be less than 26 states in the synch
  graph, which is well below 7 x 6 x 3. ?

23
Guestimating SG - contd
24
And the triple-write property?

• Can happen for really bad cases
• , sg21, (0,write), sg11, (2,write), sg13,
  (2,write), sg15,
• This is because the read cycle is between 3,5
  and the write cycle is between 2,5. So if the
  sensor is having a good day, and the monitor a
  bad one, we can miss out.
• But this is not necessarily obvious from
  eye-balling the model, as ones first thought
  might be that since 222 gt 5 we should be safe

25
What can we do?

• Need to bring the two interval ends closer.
• get the reading cycle down to 3s or
• add a choke to the writing cycle for an extra 1s
• Unless both ranges are constant, we can always
  fire the first event for free (zero time), so
  the rate test is simply
• min(acycle) (n 1) gt max(bcycle)

26
What next?