CS 644: Computer Architecture

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CHAPTER 5 MEMORY
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Who Cares About the Memory Hierarchy?

• Processor Only Thus Far in Course
• CPU cost/performance, ISA, Pipelined Execution
• CPU-DRAM Gap
• 1980 no cache in µproc 1995 2-level cache on
  chip(1989 first Intel µproc with a cache on chip)

µProc 60/yr.
1000
CPU
Moores Law
100
Processor-Memory Performance Gap(grows 50 /
year)
Performance
10
DRAM 7/yr.
DRAM
1
1980
1981
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
1982
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Processor-Memory Performance Gap Tax

• Processor Area Transistors
• (cost) (power)
• Alpha 21164 37 77
• StrongArm SA110 61 94
• Pentium Pro 64 88
• 2 dies per package Proc/I/D L2
• Caches have no inherent value, only try to close
  performance gap

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Generations of Microprocessors

• Time of a full cache miss in instructions
  executed
• 1st Alpha 340 ns/5.0 ns  68 clks x 2 or 136
• 2nd Alpha 266 ns/3.3 ns  80 clks x 4 or 320
• 3rd Alpha 180 ns/1.7 ns 108 clks x 6 or 648

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Levels of the Memory Hierarchy
Upper Level
Capacity Access Time Cost
Staging Xfer Unit
faster
CPU Registers 100s Bytes lt10s ns
Registers
prog./compiler 1-8 bytes
Instr. Operands
Cache K Bytes 10-100 ns 1-0.1 cents/bit
Cache
cache cntl 8-128 bytes
Blocks
Main Memory M Bytes 200ns- 500ns .0001-.00001
cents /bit
Memory
OS 512-4K bytes
Pages
Disk G Bytes, 10 ms (10,000,000 ns) 10 - 10
cents/bit
Disk
-6
-5
user/operator Mbytes
Files
Larger
Tape infinite sec-min 10
Tape
Lower Level
-8
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The Principle of Locality

• The Principle of Locality
• Program access a relatively small portion of the
  address space at any instant of time.
• Two Different Types of Locality
• Temporal Locality (Locality in Time) If an item
  is referenced, it will tend to be referenced
  again soon (e.g., loops, reuse)
• Spatial Locality (Locality in Space) If an item
  is referenced, items whose addresses are close by
  tend to be referenced soon (e.g., straightline
  code, array access)
• Last 15 years, HW relied on localilty for speed

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Memory Hierarchy Terminology

• Hit data appears in some block in the upper
  level (example Block X)
• Hit Rate the fraction of memory access found in
  the upper level
• Hit Time Time to access the upper level which
  consists of
• RAM access time Time to determine hit/miss
• Miss data needs to be retrieve from a block in
  the lower level (Block Y)
• Miss Rate 1 - (Hit Rate)
• Miss Penalty Time to replace a block in the
  upper level
• Time to deliver the block the processor
• Hit Time ltlt Miss Penalty (500 instructions on
  21264!)

Lower Level Memory
Upper Level Memory
To Processor
Blk X
From Processor
Blk Y
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Cache Measures

• Hit rate fraction found in that level
• So high that usually talk about Miss rate
• Miss rate fallacy as MIPS to CPU performance,
  miss rate to average memory access time in
  memory
• Average memory-access time Hit time Miss
  rate x Miss penalty (ns or clocks)
• Miss penalty time to replace a block from lower
  level, including time to replace in CPU
• access time time to lower level
• f(latency to lower level)
• transfer time time to transfer block
• f(BW between upper lower levels)

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Simplest Cache Direct Mapped
Memory Address
Memory
0
4 Byte Direct Mapped Cache
1
Cache Index
2
0
3
1
4
2
5
3
6

• Location 0 can be occupied by data from
• Memory location 0, 4, 8, ... etc.
• In general any memory locationwhose 2 LSBs of
  the address are 0s
• Addresslt10gt gt cache index
• Which one should we place in the cache?
• How can we tell which one is in the cache?

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8
9
A
B
C
D
E
F
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1 KB Direct Mapped Cache, 32B blocks

• For a 2 N byte cache
• The uppermost (32 - N) bits are always the Cache
  Tag
• The lowest M bits are the Byte Select (Block Size
  2 M)

0
4
31
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Cache Index
Cache Tag
Example 0x50
Byte Select
Ex 0x01
Ex 0x00
Stored as part of the cache state
Cache Data
Valid Bit
Cache Tag

0
Byte 0
Byte 1
Byte 31

1
0x50
Byte 32
Byte 33
Byte 63
2
3




31
Byte 992
Byte 1023
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Two-way Set Associative Cache

• N-way set associative N entries for each Cache
  Index
• N direct mapped caches operates in parallel (N
  typically 2 to 4)
• Example Two-way set associative cache
• Cache Index selects a set from the cache
• The two tags in the set are compared in parallel
• Data is selected based on the tag result

Cache Index
Cache Data
Cache Tag
Valid
Cache Block 0



Adr Tag
Compare
0
1
Mux
Sel1
Sel0
OR
Cache Block
Hit
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Disadvantage of Set Associative Cache

• N-way Set Associative Cache v. Direct Mapped
  Cache
• N comparators vs. 1
• Extra MUX delay for the data
• Data comes AFTER Hit/Miss
• In a direct mapped cache, Cache Block is
  available BEFORE Hit/Miss
• Possible to assume a hit and continue. Recover
  later if miss.

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4 Questions for Memory Hierarchy

• Q1 Where can a block be placed in the upper
  level? (Block placement)
• Q2 How is a block found if it is in the upper
  level? (Block identification)
• Q3 Which block should be replaced on a miss?
  (Block replacement)
• Q4 What happens on a write? (Write strategy)

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Q1 Where can a block be placed in the upper
level?

• Block 12 placed in 8 block cache
• Fully associative, direct mapped, 2-way set
  associative
• S.A. Mapping Block Number Modulo Number Sets

Memory
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Q2 How is a block found if it is in the upper
level?

• Tag on each block
• No need to check index or block offset
• Increasing associatively shrinks index, expands
  tag

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Q3 Which block should be replaced on a miss?

• Easy for Direct Mapped
• Set Associative or Fully Associative
• Random
• LRU (Least Recently Used)
• Associativity 2-way 4-way 8-way
• Size LRU Random LRU Random LRU Random
• 16 KB 5.2 5.7 4.7 5.3 4.4 5.0
• 64 KB 1.9 2.0 1.5 1.7 1.4 1.5
• 256 KB 1.15 1.17 1.13 1.13 1.12 1.12

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Q4 What happens on a write?

• Write throughThe information is written to both
  the block in the cache and to the block in the
  lower-level memory.
• Write backThe information is written only to the
  block in the cache. The modified cache block is
  written to main memory only when it is replaced.
• is block clean or dirty?
• Pros and Cons of each?
• WT read misses cannot result in writes
• WB no repeated writes to same location
• WT always combined with write buffers so that
  dont wait for lower level memory

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Write Buffer for Write Through
Cache
Processor
DRAM
Write Buffer

• A Write Buffer is needed between the Cache and
  Memory
• Processor writes data into the cache and the
  write buffer
• Memory controller write contents of the buffer
  to memory
• Write buffer is just a FIFO
• Typical number of entries 4
• Works fine if Store frequency (w.r.t. time) ltlt
  1 / DRAM write cycle
• Memory system designers nightmare
• Store frequency (w.r.t. time) -gt 1 / DRAM
  write cycle
• Write buffer saturation

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Impact of Memory Hierarchy on Algorithms

• Today CPU time is a function of (ops, cache
  misses) vs. just f(ops)What does this mean to
  Compilers, Data structures, Algorithms?
• The Influence of Caches on the Performance of
  Sorting by A. LaMarca and R.E. Ladner.
  Proceedings of the Eighth Annual ACM-SIAM
  Symposium on Discrete Algorithms, January, 1997,
  370-379.
• Quicksort fastest comparison based sorting
  algorithm when all keys fit in memory
• Radix sort also called linear time sort
  because for keys of fixed length and fixed radix
  a constant number of passes over the data is
  sufficient independent of the number of keys
• For Alphastation 250, 32 byte blocks, direct
  mapped L2 2MB cache, 8 byte keys, from 4000 to
  4000000

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Quicksort vs. Radix as vary number keys
Instructions
Radix sort
Quick sort
Instructions/key
Set size in keys
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Quicksort vs. Radix as vary number keys Instrs
Time
Radix sort
Time
Quick sort
Instructions
Set size in keys
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Quicksort vs. Radix as vary number keys Cache
misses
Radix sort
Cache misses
Quick sort
Set size in keys
What is proper approach to fast algorithms?
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Cache Performance

• CPU time (CPU execution clock cycles Memory
  stall clock cycles) x clock cycle time
• Memory stall clock cycles
• (Reads x Read miss rate x Read miss penalty
  Writes x Write miss rate x Write miss penalty)
• Memory stall clock cycles Memory accesses x
  Miss rate x Miss penalty

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Cache Performance

• CPUtime Instruction Count x (CPIexecution Mem
  accesses per instruction x Miss rate x Miss
  penalty) x Clock cycle time
• Misses per instruction Memory accesses per
  instruction x Miss rate
• CPUtime IC x (CPIexecution Misses per
  instruction x Miss penalty) x Clock cycle time

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Reducing Misses

• Classifying Misses 3 Cs
• CompulsoryThe first access to a block is not in
  the cache, so the block must be brought into the
  cache. Also called cold start misses or first
  reference misses.(Misses in even an Infinite
  Cache)
• CapacityIf the cache cannot contain all the
  blocks needed during execution of a program,
  capacity misses will occur due to blocks being
  discarded and later retrieved.(Misses in Fully
  Associative Size X Cache)
• ConflictIf block-placement strategy is set
  associative or direct mapped, conflict misses (in
  addition to compulsory capacity misses) will
  occur because a block can be discarded and later
  retrieved if too many blocks map to its set. Also
  called collision misses or interference
  misses.(Misses in N-way Associative, Size X
  Cache)

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3Cs Absolute Miss Rate (SPEC92)
Conflict
Compulsory vanishingly small
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21 Cache Rule
miss rate 1-way associative cache size X
miss rate 2-way associative cache size X/2
Conflict
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3Cs Relative Miss Rate
Conflict
Flaws for fixed block size Good insight gt
invention
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How Can Reduce Misses?

• 3 Cs Compulsory, Capacity, Conflict
• In all cases, assume total cache size not
  changed
• What happens if
• 1) Change Block Size Which of 3Cs is obviously
  affected?
• 2) Change Associativity Which of 3Cs is
  obviously affected?
• 3) Change Compiler Which of 3Cs is obviously
  affected?

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1. Reduce Misses via Larger Block Size
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2. Reduce Misses via Higher Associativity

• 21 Cache Rule
• Miss Rate DM cache size N Miss Rate 2-way cache
  size N/2
• Beware Execution time is only final measure!
• Will Clock Cycle time increase?
• Hill 1988 suggested hit time for 2-way vs.
  1-way external cache 10, internal 2

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Example Avg. Memory Access Time vs. Miss Rate

• Example assume CCT 1.10 for 2-way, 1.12 for
  4-way, 1.14 for 8-way vs. CCT direct mapped
• Cache Size Associativity
• (KB) 1-way 2-way 4-way 8-way
• 1 2.33 2.15 2.07 2.01
• 2 1.98 1.86 1.76 1.68
• 4 1.72 1.67 1.61 1.53
• 8 1.46 1.48 1.47 1.43
• 16 1.29 1.32 1.32 1.32
• 32 1.20 1.24 1.25 1.27
• 64 1.14 1.20 1.21 1.23
• 128 1.10 1.17 1.18 1.20
• (blue means A.M.A.T. not improved by more
  associativity)

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3. Reducing Misses via aVictim Cache

• How to combine fast hit time of direct mapped
  yet still avoid conflict misses?
• Add buffer to place data discarded from cache
• Jouppi 1990 4-entry victim cache removed 20
  to 95 of conflicts for a 4 KB direct mapped data
  cache
• Used in Alpha, HP machines

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4. Reducing Misses via Pseudo-Associativity

• How to combine fast hit time of Direct Mapped and
  have the lower conflict misses of 2-way SA cache?
  
• Divide cache on a miss, check other half of
  cache to see if there, if so have a pseudo-hit
  (slow hit)
• Drawback CPU pipeline is hard if hit takes 1 or
  2 cycles
• Better for caches not tied directly to processor
  (L2)
• Used in MIPS R1000 L2 cache, similar in UltraSPARC

Hit Time
Miss Penalty
Pseudo Hit Time
Time
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5. Reducing Misses by Hardware Prefetching of
Instructions Data

• E.g., Instruction Prefetching
• Alpha 21064 fetches 2 blocks on a miss
• Extra block placed in stream buffer
• On miss check stream buffer
• Works with data blocks too
• Jouppi 1990 1 data stream buffer got 25 misses
  from 4KB cache 4 streams got 43
• Palacharla Kessler 1994 for scientific
  programs for 8 streams got 50 to 70 of misses
  from 2 64KB, 4-way set associative caches
• Prefetching relies on having extra memory
  bandwidth that can be used without penalty

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6. Reducing Misses by Software Prefetching Data

• Data Prefetch
• Load data into register (HP PA-RISC loads)
• Cache Prefetch load into cache (MIPS IV,
  PowerPC, SPARC v. 9)
• Special prefetching instructions cannot cause
  faultsa form of speculative execution
• Issuing Prefetch Instructions takes time
• Is cost of prefetch issues lt savings in reduced
  misses?
• Higher superscalar reduces difficulty of issue
  bandwidth

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7. Reducing Misses by Compiler Optimizations

• McFarling 1989 reduced caches misses by 75 on
  8KB direct mapped cache, 4 byte blocks in
  software
• Instructions
• Reorder procedures in memory so as to reduce
  conflict misses
• Profiling to look at conflicts(using tools they
  developed)
• Data
• Merging Arrays improve spatial locality by
  single array of compound elements vs. 2 arrays
• Loop Interchange change nesting of loops to
  access data in order stored in memory
• Loop Fusion Combine 2 independent loops that
  have same looping and some variables overlap
• Blocking Improve temporal locality by accessing
  blocks of data repeatedly vs. going down whole
  columns or rows

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Summary of Compiler Optimizations to Reduce Cache
Misses (by hand)
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Summary

• 3 Cs Compulsory, Capacity, Conflict Misses
• Reducing Miss Rate
• 1. Reduce Misses via Larger Block Size
• 2. Reduce Misses via Higher Associativity
• 3. Reducing Misses via Victim Cache
• 4. Reducing Misses via Pseudo-Associativity
• 5. Reducing Misses by HW Prefetching Instr, Data
• 6. Reducing Misses by SW Prefetching Data
• 7. Reducing Misses by Compiler Optimizations
• Remember danger of concentrating on just one
  parameter when evaluating performance

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Review Improving Cache Performance

• 1. Reduce the miss rate,
• 2. Reduce the miss penalty, or
• 3. Reduce the time to hit in the cache.

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A Modern Memory Hierarchy

• By taking advantage of the principle of locality
• Present the user with as much memory as is
  available in the cheapest technology.
• Provide access at the speed offered by the
  fastest technology.

Processor
Control
Tertiary Storage (Disk/Tape)
Secondary Storage (Disk)
Main Memory (DRAM)
Second Level Cache (SRAM)
On-Chip Cache
Datapath
Registers
1s
10,000,000s (10s ms)
Speed (ns)
10s
100s
10,000,000,000s (10s sec)
100s
Size (bytes)
Ks
Ms
Gs
Ts
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Basic Issues in VM System Design
size of information blocks that are transferred
from secondary to main storage (M) block
of information brought into M, and M is full,
then some region of M must be released to
make room for the new block --gt replacement
policy which region of M is to hold the new
block --gt placement policy missing item
fetched from secondary memory only on the
occurrence of a fault --gt demand load
policy
disk
mem
cache
reg
pages
frame
Paging Organization virtual and physical address
space partitioned into blocks of equal size
page frames
pages
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Value of Hit Under Miss for SPEC
0-gt1 1-gt2 2-gt64 Base
Hit under n Misses
Integer
Floating Point

• FP programs on average AMAT 0.68 -gt 0.52 -gt
  0.34 -gt 0.26
• Int programs on average AMAT 0.24 -gt 0.20 -gt
  0.19 -gt 0.19
• 8 KB Data Cache, Direct Mapped, 32B block, 16
  cycle miss

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Comparing Local and Global Miss Rates

• 32 KByte 1st level cacheIncreasing 2nd level
  cache
• Global miss rate close to single level cache rate
  provided L2 gtgt L1
• Dont use local miss rate
• L2 not tied to CPU clock cycle!
• Cost A.M.A.T.
• Generally Fast Hit Times and fewer misses
• Since hits are few, target miss reduction

Linear
Cache Size
Log
Cache Size
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Reducing Misses Which apply to L2 Cache?

• Reducing Miss Rate
• 1. Reduce Misses via Larger Block Size
• 2. Reduce Conflict Misses via Higher
  Associativity
• 3. Reducing Conflict Misses via Victim Cache
• 4. Reducing Conflict Misses via
  Pseudo-Associativity
• 5. Reducing Misses by HW Prefetching Instr, Data
• 6. Reducing Misses by SW Prefetching Data
• 7. Reducing Capacity/Conf. Misses by Compiler
  Optimizations

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L2 cache block size A.M.A.T.

• 32KB L1, 8 byte path to memory

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Reducing Miss Penalty Summary

• Five techniques
• Read priority over write on miss
• Subblock placement
• Early Restart and Critical Word First on miss
• Non-blocking Caches (Hit under Miss, Miss under
  Miss)
• Second Level Cache
• Can be applied recursively to Multilevel Caches
• Danger is that time to DRAM will grow with
  multiple levels in between
• First attempts at L2 caches can make things
  worse, since increased worst case is worse

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What is the Impact of What Youve Learned About
Caches?

• 1960-1985 Speed ƒ(no. operations)
• 1990
• Pipelined Execution Fast Clock Rate
• Out-of-Order execution
• Superscalar Instruction Issue
• 1998 Speed ƒ(non-cached memory accesses)
• Superscalar, Out-of-Order machines hide L1 data
  cache miss (5 clocks) but not L2 cache miss
  (50 clocks)?

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Cache Optimization Summary

• Technique MR MP HT Complexity
• Larger Block Size 0Higher
  Associativity 1Victim Caches 2Pseudo-As
  sociative Caches 2HW Prefetching of
  Instr/Data 2Compiler Controlled
  Prefetching 3Compiler Reduce Misses 0
• Priority to Read Misses 1Subblock Placement
  1Early Restart Critical Word 1st
  2Non-Blocking Caches 3Second Level
  Caches 2

miss rate
miss penalty
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Address Map
V 0, 1, . . . , n - 1 virtual address
space M 0, 1, . . . , m - 1 physical address
space MAP V --gt M U 0 address mapping
function
n gt m
MAP(a) a' if data at virtual address a is
present in physical
address a' and a' in M 0 if
data at virtual address a is not present in M
a
missing item fault
Name Space V
fault handler
Processor
0
Secondary Memory
Addr Trans Mechanism
Main Memory
a
a'
physical address
OS performs this transfer
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Paging Organization
V.A.
P.A.
unit of mapping
frame 0
0
1K
Addr Trans MAP
0
1K
page 0
1
1024
1K
1024
1
1K
also unit of transfer from virtual to physical
memory
7
1K
7168
Physical Memory
31
1K
31744
Virtual Memory
Address Mapping
10
VA
page no.
disp
Page Table
Page Table Base Reg
Access Rights
actually, concatenation is more likely
V

PA
index into page table
table located in physical memory
physical memory address
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Virtual Address and a Cache
miss
VA
PA
Trans- lation
Cache
Main Memory
CPU
hit
data
It takes an extra memory access to translate VA
to PA This makes cache access very expensive,
and this is the "innermost loop" that you want
to go as fast as possible ASIDE Why access
cache with PA at all? VA caches have a problem!
synonym / alias problem two different
virtual addresses map to same physical
address gt two different cache entries holding
data for the same physical address!
for update must update all cache entries with
same physical address or memory becomes
inconsistent determining this requires
significant hardware, essentially an
associative lookup on the physical address tags
to see if you have multiple hits or
software enforced alias boundary same lsb of VA
PA gt cache size
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TLBs
A way to speed up translation is to use a special
cache of recently used page table entries
-- this has many names, but the most
frequently used is Translation Lookaside Buffer
or TLB
Virtual Address Physical Address Dirty Ref
Valid Access
Really just a cache on the page table
mappings TLB access time comparable to cache
access time (much less than main memory
access time)
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Translation Look-Aside Buffers
Just like any other cache, the TLB can be
organized as fully associative, set
associative, or direct mapped TLBs are usually
small, typically not more than 128 - 256 entries
even on high end machines. This permits
fully associative lookup on these machines.
Most mid-range machines use small n-way
set associative organizations.
hit
miss
VA
PA
TLB Lookup
Cache
Main Memory
CPU
Translation with a TLB
hit
miss
Trans- lation
data
t
20 t
1/2 t
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Reducing Translation Time

• Machines with TLBs go one step further to reduce
  cycles/cache access
• They overlap the cache access with the TLB
  access
• high order bits of the VA are used to look in
  the TLB while low order bits are used as index
  into cache

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Overlapped Cache TLB Access
Cache
TLB
index
assoc lookup
1 K
32
4 bytes
10
2
00
Hit/ Miss
PA
Data
PA
Hit/ Miss
12
20
page
disp

IF cache hit AND (cache tag PA) then deliver
data to CPU ELSE IF cache miss OR (cache tag
PA) and TLB hit THEN access
memory with the PA from the TLB ELSE do standard
VA translation
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Problems With Overlapped TLB Access
Overlapped access only works as long as the
address bits used to index into the cache
do not change as the result of VA
translation This usually limits things to small
caches, large page sizes, or high n-way set
associative caches if you want a large
cache Example suppose everything the same
except that the cache is increased to 8 K
bytes instead of 4 K
11
2
cache index
00
This bit is changed by VA translation, but is
needed for cache lookup
12
20
virt page
disp
Solutions go to 8K byte page sizes
go to 2 way set associative cache or SW
guarantee VA13PA13
2 way set assoc cache
1K
10
4
4
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Summary 1/4

• The Principle of Locality
• Program access a relatively small portion of the
  address space at any instant of time.
• Temporal Locality Locality in Time
• Spatial Locality Locality in Space
• Three Major Categories of Cache Misses
• Compulsory Misses sad facts of life. Example
  cold start misses.
• Capacity Misses increase cache size
• Conflict Misses increase cache size and/or
  associativity. Nightmare Scenario ping pong
  effect!
• Write Policy
• Write Through needs a write buffer. Nightmare
  WB saturation
• Write Back control can be complex

63
Summary 2 / 4 The Cache Design Space

• Several interacting dimensions
• cache size
• block size
• associativity
• replacement policy
• write-through vs write-back
• write allocation
• The optimal choice is a compromise
• depends on access characteristics
• workload
• use (I-cache, D-cache, TLB)
• depends on technology / cost
• Simplicity often wins

Cache Size
Associativity
Block Size
Bad
Factor A
Factor B
Good
Less
More
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Summary 3/4 TLB, Virtual Memory

• Caches, TLBs, Virtual Memory all understood by
  examining how they deal with 4 questions 1)
  Where can block be placed? 2) How is block found?
  3) What block is repalced on miss? 4) How are
  writes handled?
• Page tables map virtual address to physical
  address
• TLBs are important for fast translation
• TLB misses are significant in processor
  performance
• funny times, as most systems cant access all of
  2nd level cache without TLB misses!

65
Summary 4/4 Memory Hierachy

• VIrtual memory was controversial at the time
  can SW automatically manage 64KB across many
  programs?
• 1000X DRAM growth removed the controversy
• Today VM allows many processes to share single
  memory without having to swap all processes to
  disk today VM protection is more important than
  memory hierarchy
• Today CPU time is a function of (ops, cache
  misses) vs. just f(ops)What does this mean to
  Compilers, Data structures, Algorithms?

66
Review Four Questions for Memory Hierarchy
Designers

• Q1 Where can a block be placed in the upper
  level? (Block placement)
• Fully Associative, Set Associative, Direct Mapped
• Q2 How is a block found if it is in the upper
  level? (Block identification)
• Tag/Block
• Q3 Which block should be replaced on a miss?
  (Block replacement)
• Random, LRU
• Q4 What happens on a write? (Write strategy)
• Write Back or Write Through (with Write Buffer)