Massachusetts Institute of Technology

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Massachusetts Institute of Technology Department
of Electrical Engineering and Computer
Science 6.131 Power Electronics
Laboratory Lecture 22 November 1, 2005
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Here is your basic three phase bridge
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Suppose we have this situation
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Here is one way of switching that circuit The
arrows designate when a switch is ON
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Here is what is on in State 0
Va V, Vb V, Vc 0 Vn 2V/3
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Here is what is on in State 1
Va 0, Vb V, Vc 0 Vn V/3
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Here is what is on in State 2
Va 0, Vb V, Vc V Vn 2V/3
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Here is what is on in State 3
Va 0, Vb 0, Vc V Vn V/3
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Here is what is on in State 4
Va V, Vb 0, Vc V Vn 2V/3
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Here is what is on in State 5
Va V, Vb 0, Vc 0 Vn V/3
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Voltages Line-Line Voltages are well defined
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• To generate switching signals
• Totem Pole A is High in states 0, 4 and 5
• Totem Pole B is High in states 0, 1 and 2
• Totem Pole C is High in states 2, 3 and 4
• This allows us to use very simple logic
• A S0 S4 S5
• B S0 S1 S2
• C S2 S3 S4

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To generate switch signals Note that either top
or bottom switch is on in each phase Generation
of states we will do this a bit later (see below)
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• This six pulse switching strategy
• Makes good use of the switching devices
• Also requires shoot-through delays
• Has very simple logic
• We propose an alternative switching strategy
• Makes minimally less effective use of switches
• Uses a little more logic
• But does not risk shoot through

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Here is a comparison of switching strategies
180 degree six-pulse 120 degree six pulse Give
up a little timing between switch closings
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Switches Q_1 and Q_5 are on State0
Va V, Vb 0, Vc V/2
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Switches Q_1 and Q_6 are on State1
Va V, Vc 0, Vb V/2
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Switches Q_2 and Q_6 are on State2
Vb V, Vc 0, Va V/2
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Switches Q_2 and Q_4 are on State3
Va 0, Vb V, Vc V/2
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Switches Q_3 and Q_4 are on State4
Va 0, Vc V, Vb V/2
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Switches Q_3 and Q_5 are on State5
Vc V, Vb 0, Va V/2
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This switching pattern results in these voltages
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Switches turn on Q1 State_0 OR
State_1 Q2 State_2 OR State_3 Q3 State_4 OR
State_5 Q4 State_3 OR State_4 Q5 State_1 OR
State_5 Q6 State_1 OR State_2 Each switch is on
for two states
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So here is how to do it 3 bit input to 138
selects one of 8 outputs Active low
output! 138 has 3 enable inputs two low, one
high
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NAND (Not AND) Is the same as Negative Input OR
The 138 output is active low Matching
bubbles makes an OR function
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Now we must generate six states in sequence If we
have a clock with rising edges at the right
time interval we can use a very simple finite
state machine This could be a counter, reset when
it sees 5
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Here is a good counter to use 74LS163 This is a
loadable counter dont need that feature Clear
function is synchronous so it clears only ON a
clock edge Part is edge triggered changes
state on a positive clock edge P and T are
enables must pull them high
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And here are the counter states note how CL works
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We already detect state 5 with the 138
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The 138 is a simple selector use like this
And here are the pinouts of the 163 and 138
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Variable Voltage do the Pulse Width Modulation
thing
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Why do we need to PWM only the top switches? What
happens with you turn OFF switch Q1?