Computer Architecture What Does It Mean?? ?

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Topic IIaInstruction Set Architecture and MIPS
Introduction to Computer Systems
Engineering (CPEG 323)
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Reading List

• Slides Topic2a
• Henn Patt Chapter 2
• Other papers as assigned in class or homeworks

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MIPS R2000 CPU and FPU
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MIPS R4000 Processor Internal Block Diagram
System Control
S-Cache Controller
Data Cache
P-Cache Controller
Instruction Cache
CP0
CPU
FPU
CPU Registers
FPU Registers
Exception / Control Registers
ALU
Pipeline Bypass
Load Aligner / Store Driver
FP Multiplier
Memory Management Registers
FP Divider
Integer Multiplier / Divider
FP add convert sq root
Translation Look-Aside Buffer
Address Unit
PC Incrementer
Pipeline Control
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Registers

• 32 regs with R0 0
• Reserved registers R1, R26, R27.
• Special usage
• R28 pointer to global area
• R29 stack pointer
• R30 frame pointer
• R31 return address

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Standard Register Conventions

• The 32 integer registers in the MIPS are
  general-purpose any can be used as an operand
  or result of an arithmetic op
• But making different pieces of software work
  together is easier if certain conventions are
  followed concerning which registers are to be
  used for what purposes.
• These conventions are usually suggested by the
  vendor and supported by the compilers

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Register Conventions in the MIPS
Names Regs Purpose
zero 0 Constant 0
- 1 (Reserved for assembler)
v0-v1 2-3 Return values/expression eval
a0-a3 4-7 Args to functions
t0-t9 8-15, 24-25 Temporaries (NOT SAVED)
s0-s7 16-23 Saved values
- 26-27 (Reserved for OS kernel)
gp 28 Global pointer
sp 29 Stack pointer
fp 30 Frame pointer
ra 31 Return address
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MIPS registers and usage convention
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MIPS Operations

• Load/Store
• ALU ops
• Branches/Jumps

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MIPS Instruction Formats
R-Format
op
rs
rt
rd
shamt
funct
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
I-Format
op
rs
rt
address
6 bits
5 bits
5 bits
16 bits
J-Format
op
address
6 bits
26 bits
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Fields in MIPS Instructions

• op Specifies the operation tells which format
  to use
• rs First source register
• rt second source register (or dest. For load)
• rd Destination register
• shamt Shift amount (described later)
• funct Further elaboration on opcode
• address immediate constant, displacement, or
  branch target

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Machine Representation of MIPS Insrtuctions
MIPS fields are given names to make them easier
to discuss

• Here is the meaning of each name of the fields in
  MIPS
• instructions
• op operation of the instruction
• rs the first register source operand
• rt the second register source operand
• rd the register destination operand it gets
  the result of the operation
• shamt shift amount
• funct function this field selects the
  variant of the operation in the op field

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ALU ops

• R-type
• ADD R1,R2,R3
• effect R1 R2 R3
• Example (in MIPS assembler form)
• ADD t0, s1, s2

Decimal representation 0 17 18 8 0 32
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Machine representation (contd)

• Decimal representation

Binary representation
10010
01000
00000
10001
000000
100000
6 bits 5 bits 5 bits 5 bits
5 bits 6 bits
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Integer Multiply and Divide in MIPS

• Multiplying two 32-bit numbers can result in up
  to 64 bits
• Integer division creates a quotient and remainder
• MIPS has two special regs hi and lo
• Multiply results lower bits go to lo, upper to
  hi
• Divide results quotient goes to lo, remainder to
  hi
• Use extra ops (such as mflo) to move lo hi to
  GPRs.

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Data Transfer Instructions

• I-type (base 16 bit offsets)

address
op
rs
rt
6 bits 5 bits 5 bits
16 bits
base
dest
offset
Example lw t0, 8 (s3) --- Temporary reg t0
gets A8 Note s3 stores the start address of
array A Also, rs is the base register (S3 in
this case also called index register), rt (in
this case t0) stores the result (as destination
register).
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MIPS Does A(BC)(DE)
An Example

• Assembly
• lw 8, 48(0)
• lw 9, 76(0)
• add 8, 8, 9
• lw 9, 20(0)
• lw 10, 32(0)
• add 9, 9, 10
• add 8, 8, 9
• sw 8, 100(0)

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Branches

• In most processors, the Program Counter (PC)
  holds the address of the next instruction fetch
  from M(PC)
• Normally, after an instruction is finished, the
  CPU adds n to the PC, where n is the number of
  bytes in the instruction.
• Branches allow a program to start fetching from a
  different place.
• Branches are used to implement all the
  control-flow commands of high-level languages,
  such as if-then-else, for, switch, etc.

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Branch Classification

• Two basic types of branches
• Unconditional Always jump to the specified
  address
• Conditional Jump to the specified address if
  some condition is true otherwise, continue with
  the next instruction
• Destination addresses can be specified in the
  same way as other operands (combination of
  registers, immediate constants, and memory
  locations), depending on what is supported in the
  ISA.

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Branch Compilation Example

• Compile the following

i j
i ? j
i j?
if ( i j) f g h else f g h
Else
f g h
f g - h
Exit
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If-Then-Else in MIPS

• Assume f,g,h,i,j in R8-R12 (respectively)
• bne 11, 12, Else Branch if iltgtj
• add 8, 9, 10 f g h
• j Exit Jump to Exit
• Else sub 8, 9, 10 f g h
• Exit Code after if

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Observation on Branches

• Most conditional branches go a short and constant
  distance
• Fancy addressing modes not often used
• No use for auto-increment/decrement
• So in keeping with the RISC philosophy of
  simplicity, MIPS has only a few basic branch
  types.

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MIPS Branch Types

• Conditional branch beq/bne reg1, reg2, addr
• - If reg1 /? reg2, jump to PC addr
  (PC-relative)
• Register jump jr reg
• - Fetch address from specified register, and
  jump to it
• Unconditional branch j addr
• - Always jump to addr (use pseudodirect
  addressing)

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Generating Branch Targets in MIPS
4 PC-relative addressing
Memory
op
rt
rs
Address
Word
PC

5 Pseudodirect addressing
Memory
op
Address
Word

PC
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Branch Instructions

• Conditional branches
• - beq R1, R2, L1 if R1 R2 go to L1
• - bne R1, R2, L1 if R1 \ R2 go to L1
• These are R-type instructions
• Unconditional branches
• JR R8 Jump based on register 8
• Test if lt 0
• slt R1, R16, R17 R1 gets 1 if R16 lt
  R17
• (slt set-less-than)
• bne R1, 0, less branch to less if R1 \ 0

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Compiling Other Control Statements

• Loops
• for, while test before loop body jump past loop
  body if false
• Do test condition at end of loop body jump to
  beginning if true
• Switch (called case statements in some other
  languages)
• Build a table of addresses
• Use jr (or equiv. In non-MIPS processor)
• Be sure to check for default and unused cases!

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Switch Compilation Example

• Compile the following
• switch (k)
• case 0 f f 1 break
• case 1 f f 2 break
• case 3 f -f break
• Note the gap (case 2)

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Switch Body in MIPS

• L0 addi 8, 8, 1 add immed. 1 to r8 (f)
• j Exit jump to Exit (break)
• L1 subi 8, 8, 2 subtract imm. 2 from r8
• j Exit Another break
• L3 sub 8, 0, 8 f 0 - f
• j Exit Another break
• Build the lookup table in memory

1000 1004 1008 1012
address of L0
address of L1
address of Exit
address of L3
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Switch Compiled for MIPS

• (Assume k in r13)
• slti 14, 13, 0 set r14 if r13 lt 0
• bne 14, 0, Exit Go to Exit if k lt 0
• slti 14, 13, 4 set r14 if k lt 4
• beq 14, 0, Exit Go to Exit if k ? 4
• add 14, 13, 13 r14 2k
• add 14, 14, 14 r14 4k
• lw 14, 1000 (14) Base of table at 1000
• jr 14 Jump to the address

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Instructions Supporting Procedure Calls

• Jump and link
• jal procedure address
• note return address is stored in R31
• Return
• jr R31
• Saving return address on stack
• R29 is used as stack pointer
• Parameter passing
• R4 R7 are used for these

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Other MIPS Addressing Style

• Constant or immediate operands
• lw R24, AddrConstant4(0)
• addi R3, R4, 5 (I type)
• constants are 16-bit long
• lui R8 255 load-upper-immediate
• J-type
• J 10000 goto location 10000

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MIPS operands
MIPS assembly language
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MIPS machine language
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Function Calls in the MIPS

• Function calls an essential feature of
  programming languages
• The program calls a function to perform some task
• When the function is done, the CPU continues
  where it left off in the calling program
• But how do we know where we left off?

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Calling a Function in the MIPS

• Use the jal (jump and link) instruction
• jal addr just like j addr except
• The return address (PC) 4 placed in R31
• This is the address of the next instruction after
  the jal
• Use jr 31 to return

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Call Example

• Caller Callee
• add 4, 0, 1000 F lw 6, 0(4)
• add 5, 0, 1200 lw 7, 0(5)
• add 1, 0, 1 sw 6, 0(5)
• sw 1, 0(4) sw 7, 0(4)
• add 1, 1, 1 jr 31
• sw 1, 0 (5)
• jal F
• sub 1, 1, 2
• What does F do?

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Difficulties with Function Calls

• This example works OK. But what if
• The function F calls another function?
• The caller had something important in regs R6
  and/or R7?
• The called function calls itself?
• Each version of a function should have its own
  copies of variables
• These are arranged in a stack, as a pile of
  frames.

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Stack Example

• Assume function A calls B, which calls C.
  Function C calls itself once

Ds vars
Cs vars
Cs vars
Bs vars
Bs vars
Bs vars
As vars
As vars
As vars
start A
A calls B
B calls C
C calls D